Study of high-tech process furnace using inherently safer design strategies (III) advanced thin film process and reduction of power consumption
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- 作者：Chih-Cheng Lua ; Kuo-Chi Changa ; Chun-Yu Chenb ; chency1617@gmail.com" class="auth_mail" title="E-mail the corresponding author
- 关键词：Inherently safer design ; LPCVD ; Thin film deposition ; 22 nm IC process ; Reduction of power consumption ; FMEA
- 刊名：Journal of Loss Prevention in the Process Industries
- 出版年：2016
- 出版时间：September 2016
- 年：2016
- 卷：43
- 期：Complete
- 页码：280-291
- 全文大小：3179 K
文摘
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Summarized the current 22 nm advanced semiconductor process and integration design of element processes.
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Conducted hazard analysis of current 22 nm advanced semiconductor process, tools, and facility by using FMEA.
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Proposed the CVD thin film deposition of TEOS (tetraethyl orthosilicate) process conditions.
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Proposed the IPD process applied on the 22 nm MOSFETs, with a thickness of 5000 Å and process time of 60 min.
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Reduction of power consumption satisfied the attenuation strategy of ISD and converted power output up to 3971 W.