Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip

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• 作者：Sayed T. Muhammad^a ; ^{sayed.taha@eng.bsu.edu.eg}Author Vitae ; Magdy A. El-Moursy^b ; ^c ; ^{magdy_el-moursy@mentor.com}Author Vitae ; Ali A. El-Moursy^d ; ^{aelmoursy@sharjah.ac.ae}Author Vitae ; Hesham F.A. Hamed^e ; ^{hfah66@yahoo.com}Author Vitae
• 关键词：NoC ; Process variation ; Throughput ; Asynchronous router ; Synchronous router ; Clock skew ; Architecture level simulator
• 刊名：Journal of Parallel and Distributed Computing
• 出版年：2017
• 出版时间：April 2017
• 年：2017
• 卷：102
• 期：Complete
• 页码：175-185
• 全文大小：1988 K
• 卷排序：102

文摘

At System Level, interconnect PV delay is not ignorable anymore (9% of total delay). Clock skew represents 32% of total NoC delay for synchronous NoCs at System Level. Throughput reduction for asynchronous NoC is less than half that of synchronous NoC. Asynchronous design can better adapt to PV as compared to synchronous design. Technology scaling perf. variation of System-Level is similar to Circuit analysis.