Fast clock scheduling and an application to clock tree synthesis

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• 作者：Rickard Ewetz ; ^{rewetz@purdue.edu} ; Cheng-Kok Koh ^{chengkok@purdue.edu}
• 关键词：Algorithms ; Clock network synthesis ; Low-power ; Physical design ; Skew
• 刊名：Integration, the VLSI Journal
• 出版年：2017
• 出版时间：January 2017
• 年：2017
• 卷：56
• 期：Complete
• 页码：115-127
• 全文大小：1064 K
• 卷排序：56

文摘

Clock networks are required to be constructed with adequate safety margins in the skew constraints to operate correctly even under the influence of variations. In this work, a scalable clock scheduler is developed to drive a synthesis framework that constructs useful skew clock trees with large safety margins that are tailored to the tree topology. Sequential elements are clustered early in the topology, if it is impossible provide adequate robustness to variations using only safety margins. Compared to earlier studies, the proposed framework performs the clock scheduling one to two orders of magnitude faster and improves yield and capacitive cost on several synthesized circuits.