FPGA Implementation of Area-Efficient IEEE 754 Complex Divider

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• 作者：Anila Ann Varghese^a ; ^{anilaann7@gmail.com" class="auth_mail" title="E-mail the corresponding author} ; C. Pradeep^a ; Madhuri Elsa Eapen^a ; R. Radhakrishnan^b
• 关键词：Complex Division ; FPGA ; IEEE754 ; Module Reuse
• 刊名：Procedia Technology
• 出版年：2016
• 出版时间：2016
• 年：2016
• 卷：24
• 期：Complete
• 页码：1120-1126
• 全文大小：489 K

文摘

Division algorithms are less often used unlike other arithmetic operations. But it cannot be avoided in some systems to achieve some functionality. The division of complex numbers has got applications in fields like telecommunication, microwave systems, signal processing, GPS etc. This work proposes an area-efficient method for complex divider implementation on FPGA. The operands are represented in single precision floating point (IEEE754) format. A novel method called module reuse technique is used for reducing the device utilization on FPGA. The proposed design is analyzed using the simulation and implementation results on Xilinx Artix-7 and Virtex-5 FPGA families.