Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs

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• 作者：Juan Antonio Clemente^a ; Author Vitae ; Wassim Mansour^bAuthor Vitae ; Rafic Ayoubi^cAuthor Vitae ; Felipe Serrano^aAuthor Vitae ; Hortensia Mecha^aAuthor Vitae ; Haissam Ziade^dAuthor Vitae ; Wassim El Falou^dAuthor Vitae ; Raoul Velazco^bAuthor Vitae
• 关键词：Artificial Neural Network (ANN) ; Hopfield Neural Network (HNN) ; Single Event Upset (SEU) ; Single Event Transient (SET) ; FPGA ; Fault tolerance
• 刊名：Neurocomputing
• 出版年：2016
• 出版时间：1 January 2016
• 年：2016
• 卷：171
• 期：Complete
• 页码：1606-1609
• 全文大小：987 K

文摘

This letter presents an FPGA implementation of a fault-tolerant Hopfield Neural Network (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non-fault-tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.