Shared resource aware scheduling on power-constrained tiled many-core processors

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• 作者：Sudhanshu Shekhar Jha^a ; ^{sjha@ac.upc.edu}Author Vitae ; Wim Heirman^b ; ^{wim.heirman@intel.com}Author Vitae ; Ayose Falcó ; n^c ; ^{ayose.falcon@hp.com}Author Vitae ; Jordi Tubella^a ; ^{jordit@ac.upc.edu}Author Vitae ; Antonio Gonzá ; lez^a ; ^{antonio@ac.upc.edu}Author Vitae ; Lieven Eeckhout^d ; ^{lieven.eeckhout@ugent.be}Author Vitae
• 关键词：Many-core tiled architecture ; Thread migration ; Power budget ; Adaptive microarchitecture
• 刊名：Journal of Parallel and Distributed Computing
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：100
• 期：Complete
• 页码：30-41
• 全文大小：1300 K
• 卷排序：100

文摘

A low-overhead and high scalable hierarchical power manager on a tiled many-core architecture with shared LLC and VR. Shared DVFS and cache adaptation can degrade performance of co-scheduled threads on a tile. DVFS and cache-aware thread migration (DCTM) to ensure optimum per-tile co-scheduling of compatible threads at runtime. DCTM assisted hierarchical power manager improves performance by up to 20% compared to conventional centralized power manager with per-core VR.