High performance parallel turbo decoder with configurable interleaving network for LTE application
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- 作者：Zhiting YanAuthor Vitae ; Guanghui He ; guanghui.he@sjtu.edu.cn" class="auth_mail" title="E-mail the corresponding author ; heguanghui@ic.sjtu.edu.cn" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Weifeng HeAuthor Vitae ; Shuaijie WangAuthor Vitae ; Zhigang MaoAuthor Vitae
- 关键词：Long term evolution (LTE) ; Parallel turbo decoder ; Quadratic permutation polynomial (QPP) interleaver ; Add&ndash ; compare&ndash ; select (ACS)
- 刊名：Integration, the VLSI Journal
- 出版年：2016
- 出版时间：January 2016
- 年：2016
- 卷：52
- 期：Complete
- 页码：77-90
- 全文大小：4110 K
文摘
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Configurable interleaving network supports any 2i-input lick to view the MathML source">(0≤i≤n) network. A new low complexity address generator for interleaving.
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Optimized decoding schedule reduces performance loss caused by parallel turbo decoding.
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Configurable memory architecture is proposed to avoid memory access contention. Dual-mode ACS unit for both radix-2 and radix-4 processing.
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The proposed parallel turbo decoder supports all 188 block sizes in LTE.