Modelling and dimensioning of a high-radix datacentre optical packet switch with recirculating optical buffers

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• 作者：Jingyan Wang ; ^{jingyan.wang9@mail.dcu.ie" class="auth_mail" title="E-mail the corresponding author} ; Conor McArdle ^{mcardlec@eeng.dcu.ie" class="auth_mail" title="E-mail the corresponding author} ; Liam P. Barry ^{liam.barry@dcu.ie" class="auth_mail" title="E-mail the corresponding author}
• 关键词：Network modelling and dimensioning ; Markov-modulated Poisson Process ; Optical packet switch ; Arrayed Waveguide Grating ; Fibre Delay Lines
• 刊名：Optical Switching and Networking
• 出版年：2017
• 出版时间：January 2017
• 年：2017
• 卷：23
• 期：part_P1
• 页码：67-81
• 全文大小：2461 K

文摘

Recently, high port-count optical packet switches, based on the Arrayed Waveguide Grating (AWG) device, have been proposed for providing the very high bandwidth and connectivity degree that will be required in future datacentre interconnection networks. A practical, cost-effective realisation of such a switch requires that over-subscription of the AWG cross-connect output ports be allowed, with the resulting packet contention being resolved using a packet buffering facility in the switch. In this paper, we propose an efficient AWG switch architecture of this type that uses a recirculating optical packet buffering scheme and we develop analytic modelling methods to estimate the switch packet blocking probability and packet buffering delay. The analytic model resolves internal traffic flows in the switch as Markov-modulated Poisson Processes (MMPP) and also allows modelling of offered load to the switch as a MMPP process. Taking this model of the switch, we first show its accuracy compared to discrete event simulations and then use it to develop a heuristic optimisation algorithm to dimension the switch hardware components, with the objective of minimising the operating cost by optimally dimensioning the main power consuming components, subject to constraints on the maximum contention probability and average and maximum propagation delays. The resulting optimised switch design demonstrates the proposed architecture to be a promising candidate for future high-port count datacentre switches.