Heat dissipation assessment of through silicon via (TSV)-based 3D IC packaging for CMOS image sensing
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- 作者：Hsien-Chie Chenga ; hccheng@fcu.edu.tw" class="auth_mail" title="E-mail the corresponding author ; Tzu-Chin Huangb ; Po-Wen Hwanga ; Wen-Hwa Chenb ; whchen@pme.nthu.edu.tw" class="auth_mail" title="E-mail the corresponding author
- 关键词：3D IC ; Through silicon via ; Thermal performance ; Finite element modeling ; Equivalent thermal conductivity model ; Thermal experiments ; Uncertainty analysis
- 刊名：Microelectronics Reliability
- 出版年：2016
- 出版时间：April 2016
- 年：2016
- 卷：59
- 期：Complete
- 页码：84-94
- 全文大小：1970 K
文摘
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Numerical and experimental study of thermal behavior of 3D TSV IC package is made.
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SiO2 layer plays a great effect on the effective thermal conductivities of TSV chip.
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Chip junction temperature of 3D TSV IC package highly depends on power setting.
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Uniform power setting is ineffective for temperature prediction of very thin chips.
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Material and area of interposer are the factors most affecting thermal performance.
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