Threshold voltage instabilities in p-channel power VDMOSFETs under pulsed NBT stress

详细信息    查看全文

• 作者：N. Stojadinovi&#x107 ; D. Dankovi&#x107 ; I. Mani&#x107 ; A. Priji&#x107 ; V. Davidovi&#x107 ; S. Djori&#x107 ; -Veljkovi&#x107 ; S. Golubovi&#x107 ; Z. Priji&#x107
• 刊名：Microelectronics Reliability
• 出版年：2010
• 出版时间：September-November 2010
• 年：2010
• 卷：50
• 期：9-11
• 页码：1278-1282
• 全文大小：696 K

文摘

Threshold voltage instabilities induced in p-channel power VDMOSFETs by pulsed negative bias temperature stressing are presented and compared with corresponding instabilities found after the static NBT stress. Degradation observed under the pulsed stress conditions depends on the frequency and duty cycle of stress voltage pulses, and is generally lower than the one found after the static NBT stress. Optimal frequency and duty cycle ranges for application of investigated devices are proposed as well. By selecting an appropriate combination of frequency range (1&#xa0;kHz&#xa0;<&#xa0;f&#xa0;<&#xa0;5&#xa0;kHz) and duty cycle (about 25 % ), the pulsed stress-induced ΔV_T can be reduced to a quarter of ΔV_T found after the static NBT stress.