A new parallel hardware architecture for high-performance stereo matching calculation
详细信息 查看全文
- 作者：Young-Ho SeoAuthor Vitae ; Ji-Sang YooAuthor Vitae ; Dong-Wook Kim ; dwkim@kw.ac.kr" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae
- 关键词：Stereo vision ; Stereo matching ; Architecture ; Disparity ; FPGA ; Memory bandwidth
- 刊名：Integration, the VLSI Journal
- 出版年：2015
- 出版时间：September 2015
- 年：2015
- 卷：51
- 期：Complete
- 页码：81-91
- 全文大小：1397 K
文摘
- •
A H/W architecture for real-time stereo matching.
- •
Analysis of the arithmetic characteristic of stereo matching.
- •
Method to reuse the intermediate results.
- •
Method to minimize the calculation load and memory access.
- •
Expandable hardware for 1D and 2D operation.