Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits

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• 作者：Samson Melamed ; ^{samson.melamed@aist.go.jp} ; Naoya Watanabe ; Shunsuke Nemoto ; Haruo Shimamoto ; Katsuya Kikuchi ; Masahiro Aoyagi
• 关键词：3DIC ; Die thinning ; Thermal resistance ; Integrated circuit
• 刊名：Microelectronics Reliability
• 出版年：2016
• 出版时间：December 2016
• 年：2016
• 卷：67
• 期：Complete
• 页码：2-8
• 全文大小：1102 K
• 卷排序：67

文摘

In 3D integrated circuits wafer-thinning can lead to large thermal gradients. Thinning is important to decrease the size of through silicon vias. The top tier of a test chip was thinned from 725 to 20 μm. This thinning resulted in a nearly 4 × increase in the normalized temperature rise.