High performance single supply CMOS 0.45-1 V input to 1.1 V output level up shifter

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• 作者：José ; -Carlos Garcí ; a^a ; ^{jcgarcia@iuma.ulpgc.es} ; Juan A. Montiel-Nelson^a ; ^{montiel@iuma.ulpgc.es} ; S. Nooshabadi^b ; ^{saeid@mtu.edu}
• 关键词：Power supply domains ; Level shifter ; Single supply voltage ; High-speed ; Low energy consumption ; Drive capability
• 刊名：Microelectronics Journal
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：60
• 期：Complete
• 页码：82-86
• 全文大小：601 K
• 卷排序：60

文摘

This paper presents the design of a single supply CMOS level up shifter for low voltage and low energy consumption. The proposed voltage level converter is implemented using low threshold voltage transistors in 65 nm CMOS technology. The shifter circuit designed for an output of 1.1 V was verified, through the post–layout simulation, to be functional for an input voltage range of 0.45–1 V. We compare our work with several other level shifters. With a 50 fF of capacitive load, the shifter's energy–delay product is a 40% lower than a similar single supply level up shifter. Moreover, the measurements on the fabricated dies show that the proposed structure is able to drive a double capacitive load of up to 105 fF, without any impact on the static power consumption. Monte–Carlo analysis demonstrates the robustness of the proposed shifter within a 3σ device mismatch.