Low space-complexity and low power semi-systolic multiplier architectures over GF(2m) based on irreducible trinomial
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- 作者：Fayez Gebalia ; fayez@ece.uvic.ca" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Atef Ibrahim ; a ; b ; c ; atef@ece.uvic.ca" class="auth_mail" title="E-mail the corresponding author ; attif_ali2002@yahoo.com" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae
- 关键词：Trinomial multiplier ; Finite field multiplication ; Systolic arrays ; Parallel architectures ; Pipeline processing ; VLSI
- 刊名：Microprocessors and Microsystems
- 出版年：2016
- 出版时间：February 2016
- 年：2016
- 卷：40
- 期：Complete
- 页码：45-52
- 全文大小：789 K
文摘
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Propose low power bit-serial and digit-serial semi-systolic multiplier architectures over GF(2m).
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Develop a new Progressive Reduction Technique (PPR).
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Develop affine and nonlinear task scheduling functions.
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Develop affine and nonlinear task projection onto processors.
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Provide ASIC Implementation for proposed and previously published designs.