An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m)
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- 作者：Bahram Rashidia ; b.rashidi@ec.iut.ac.ir" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Sayed Masoud Sayedia ; m_sayedi@cc.iut.ac.ir" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Reza Rezaeian Farashahib ; c ; farashahi@cc.iut.ac.ir" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae
- 关键词：Cryptography ; Logical effort ; Finite fields ; Optimal normal basis multiplication ; VLSI design
- 刊名：Integration, the VLSI Journal
- 出版年：2016
- 出版时间：September 2016
- 年：2016
- 卷：55
- 期：Complete
- 页码：138-154
- 全文大小：3411 K
文摘
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Efficient hardware implementations of normal basis multipliers.
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A structural VLSI implementation of XOR tree in the multipliers.
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An optimized 4-input XOR logic gate used in XOR trees of multipliers is presented.
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The proposed XOR–AND circuit is more compact than a cascade structure.