A comprehensive reconfigurable computing approach to memory wall problem of large graph computation
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- 作者：Xu Wanga ; wang2002xu@gmail.com" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Yongxin Zhua ; b ; zhuyongxin@sjtu.edu.cn" class="auth_mail" title="E-mail the corresponding author ; yongxin.zhu@nus.edu.sg" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Linan Huanga ; huanglinan@sjtu.edu.cn" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae
- 关键词：Embedded architecture ; FPGA ; Graph computing ; Hardware implementation ; Memory wall problem
- 刊名：Journal of Systems Architecture
- 出版年：2016
- 出版时间：October 2016
- 年：2016
- 卷：70
- 期：Complete
- 页码：59-69
- 全文大小：1094 K
文摘
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The extension of the edge-streaming model with massive partitions to accelerate large graph computing in reconfigurable hardware.
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A two-level shuffle network architecture to reduce the on-chip memory requirement while provide high processing throughput.
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A compact storage designusing graph compression and a corresponding codec hardware to reduce the amount of transferred data.
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Up to 3.85 times improvement in terms of performance to bandwidth ratio over the state-of-the-art hardware implementation.