Frequency compensation of two stage CMOS circuit using negative capacitance and flipped voltage follower

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• 作者：Urvashi Bansal ; Maneesha Gupta…
• 关键词：Analog signal processing ; CMOS ; Multistage amplifier ; Passive compensation ; Negative capacitance ; Flipped voltage follower
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2017
• 出版时间：January 2017
• 年：2017
• 卷：90
• 期：1
• 页码：175-188
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing;
• 出版者：Springer US
• ISSN：1573-1979
• 卷排序：90

文摘

This paper presents a new and compact two stage CMOS structure with enhanced gain-bandwidth product (GBW) and high slew rate. The frequency compensation technique employed here comprises of a negative capacitance cell and a flipped voltage follower (FVF). The use of negative capacitance lowers the parasitic capacitance of preceding stage and thereby achieves significant improvement in GBW. The FVF acts as a voltage buffer and exploits pole-zero cancellation technique. The required compensation capacitor is very small so it can save chip area. The workability of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 µm process parameters. The simulated results show a GBW of 1.2 GHz and average slew rate of 88 V/µs with a power consumption of 6.3 mW.