A multi-objective synthesis methodology for majority/minority logic networks

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• 作者：Moein Sarvaghad-Moghaddam ; Ali A. Orouji…
• 关键词：Logic synthesis ; Majority gates ; Quantum ; dot cellular automata (QCA) ; Multi ; objective
• 刊名：Journal of Computational Electronics
• 出版年：2017
• 出版时间：March 2017
• 年：2017
• 卷：16
• 期：1
• 页码：162-179
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Appl.Mathematics/Computational Methods of Engineering; Electrical Engineering; Theoretical, Mathematical and Computational Physics; Optical and Electronic Materials; Mechanical Engineering;
• 出版者：Springer US
• ISSN：1572-8137
• 卷排序：16

文摘

New technologies such as quantum-dot cellular automata, single-electron tunneling, tunneling phase logic, and all-spin logic devices have been widely advocated in nanotechnology as a response to the physical limits associated with complementary metal–oxide–semiconductor technology at atomic scales. Some of their peculiar features are their smaller size, higher speed, higher switching frequency, lower power consumption, and higher scale integration. In these technologies, the majority (or minority) and inverter gates are employed for the production of the functions as this set of gates makes a universal set of Boolean primitives in these technologies. An important step in the generation of Boolean functions using the majority gate is reducing the number of involved gates. In this paper, a multi-objective synthesis methodology (with the objective priority of gate counts, gate levels, and the number of inverter gates) is presented for finding the minimal number of possible majority gates in the synthesis of Boolean functions using the proposed majority specification matrix (MSM) concept. Moreover, based on MSM, a synthesis flow is proposed for the synthesis of multi-output Boolean functions. To reveal the efficiency of the proposed method, it is compared with a meta-heuristic method, multi-objective genetic programing (GP). Besides, it is applied to synthesize MCNC benchmark circuits. The results are indicative of the outperformance of the proposed method in comparison to the multi-objective GP method. Also, for the MCNC benchmark circuits, there is an average reduction of 10.5% in the number of levels as well as 16.8% and 33.5% in the number of majority and inverter gates, respectively, as compared to the best available method.