Optimization of Test Wrapper for TSV Based 3D SOCs

详细信息    查看全文

• 作者：Surajit Kumar Roy ; Chandan Giri ; Hafizur Rahaman
• 关键词：3D System ; on ; Chip test ; Wrapper design ; Wrapper elements ; Test access mechanism
• 刊名：Journal of Electronic Testing
• 出版年：2016
• 出版时间：October 2016
• 年：2016
• 卷：32
• 期：5
• 页码：511-529
• 全文大小：2,162 KB
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems
  Electronic and Computer Engineering
  Computer-Aided Engineering and Design
  
• 出版者：Springer Netherlands
• ISSN：1573-0727
• 卷排序：32

文摘

Manufacturing of core based three-dimensional (3D) integrated circuit (IC) is an emerging field of semiconductor industry that promises greater number of devices on chip, increased performance and reduced power consumption. But due to scaling in technology features these chips are more complex. Hence testing of these 3D ICs is a challenging task and designing the test wrapper of core is also an important issue in this respect. This paper follows a IEEE 1500-style wrapper design for 3D ICs using Through Silicon Vias (TSVs) for testing purpose. It is assumed that the core elements are distributed over several layers of the ICs. As the number of available TSVs are limited due to small chip area, this work is intended to design balanced wrapper chains using minimum number of TSVs so that testing time of a core is reduced. In this work we have proposed a polynomial time algorithm of O(N) to design the test wrapper. The results are presented based on the ITC’02 SOC test benchmarks and compared with prior works. Obtained results show that our algorithm provides better utilization of TSVs compared to the work presented in Noia et al. (2011).