A 65 mW fully integrated UHF-band CMMB tuner in 65 nm CMOS process

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• 作者：JunHua Liu (1)
  Chen Li (2)
  Long Chen (1)
  CongYin Shi (1)
  XuanKai Weng (1)
  YiXiao Wang (1)
  JiaYi Wang (1)
  Yu Liao (1)
  Le Ye (1)
  HuaiLin Liao (1)
  Ru Huang (1)
  
• 关键词：CMMB ; digital TV ; tuner ; receiver
• 刊名：SCIENCE CHINA Information Sciences
• 出版年：2013
• 出版时间：January 2013
• 年：2013
• 卷：56
• 期：1
• 页码：1-5
• 全文大小：518KB
• 参考文献：1. CMMB-GY/T220. 7. Technical specifications for receiving and decoding terminal, SARFT. May 2008
  2. Jussila J, Sivonen P. A 1.2-V highly linear balanced noise-cancelling LNA in 0.13-μm CMOS. IEEE J Solid-State Circ, 2008, 43: 579-87 CrossRef
  3. Ye L, Shi C, Liao H, et al. A 0.47mW 6th-order 20MHz active filter using high power-efficient opamp. In: IEEE Proc Int Symp Circuits & Syst, Rio de Janeiro, 2011. 1640-643
  4. Ye L, Liao H, Song F, et al. A single-chip CMOS UHF RFID reader transceiver for Chinese mobile applications. IEEE J Solid-State Circ, 2010, 45: 1316-329 CrossRef
  5. Kang S, Kim S, Choi J H, et al. A triband 65nm CMOS tuner for ATSC mobile DTV SoC. In: Boeck G, ed. IEEE Radio Frequency Integrated Circuits Symposium, Anaheim, CA, 2010. 185-88
  6. Huang Y T, Huang S C, Pan H L, et al. A 1.2V 67mW 4mm² mobile ISDB-T tuner in 0.13μm CMOS. In: IEEE International Solid-State Circuits Conference, San Francisco, CA, 2009. 124-25, 125a
  7. Kuo M C, Kao S W, Chen C H, et al. A 1.2V 114mW dual-band direct-conversion DVB-H tuner in 0.13μm CMOS. IEEE J Solid-State Circ, 2009, 44: 740-50 CrossRef
  
• 作者单位：JunHua Liu (1)
  Chen Li (2)
  Long Chen (1)
  CongYin Shi (1)
  XuanKai Weng (1)
  YiXiao Wang (1)
  JiaYi Wang (1)
  Yu Liao (1)
  Le Ye (1)
  HuaiLin Liao (1)
  Ru Huang (1)
  
  1. Institute of Microelectronics, Peking University, Beijing, 100871, China
  2. Shanghai Integrated Circuit R&D Center Co. Ltd., Shanghai, 201210, China
  
• ISSN：1869-1919

文摘

A low power fully integrated digital TV tuner chip for China Mobile Multimedia Broadcasting (CMMB) application is presented. Based on direction conversion architecture, analog 8th-order filter/gain stages utilizing high power efficient operation-amplifiers and a ΣΔ fractional-N phase locked loop (PLL) with one voltage controlled oscillator (VCO) covering 4.8-.2 GHz is proposed for low power and small chip area. The tuner is implemented in 65 nm CMOS process with low noise amplifier (LNA) matching network and phase locked loop (PLL) filter integrated on chip, occupying a chip area of 4.83 mm2. The measured noise figure (NF) is less than 3.2 dB over CMMB UHF band (470-98 MHz). A total power consumption of 65 mW (54 mA from 1.2 V supply) is achieved.