A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET

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• 作者：Vadthiya Narendar ; Saurabh Rai ; Siddharth Tiwari
• 关键词：Drain ; induced barrier lowering (DIBL) ; Dual ; material double ; gate (DMDG) ; FinFET ; Short ; channel effects (SCEs) ; Subthreshold current ; Underlap
• 刊名：Journal of Computational Electronics
• 出版年：2016
• 出版时间：December 2016
• 年：2016
• 卷：15
• 期：4
• 页码：1316-1325
• 全文大小：1,663 KB
• 刊物类别：Engineering
• 刊物主题：Electronic and Computer Engineering
  Optical and Electronic Materials
  Mathematical and Computational Physics
  Applied Mathematics and Computational Methods of Engineering
  Mechanical Engineering
  
• 出版者：Springer Netherlands
• ISSN：1572-8137
• 卷排序：15

文摘

Double-gate (DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) are regarded as leading front-runners in the semiconductor industry. To alleviate the short-channel effects (SCEs) in the DG MOSFET, a new underlap dual-material (DM) DG FinFET device structure is proposed herein, combining the advantages of an underlapped device with those of a dual-material gate (DMG) device. Two-dimensional (2D) analytical surface potential and subthreshold current modelling of the proposed device has been done by solving Poisson’s equation. It has been found that the results obtained analytically are in good agreement with numerical simulation results. As the underlap length (\(L_\mathrm{un}\)) is increased, a substantial reduction of the subthreshold current due to enhanced gate control over the channel regime is observed. The DMG used in the structure improves the average velocity of the carriers, which leads to superior drive current for the device. The proposed device structure is compared with underlap single-material (SM) DG FinFET structure in terms of electrical characteristics, such as drain-induced barrier lowering (DIBL). This comparison confirms the suppression of SCEs with increasing \(L_\mathrm{un}\) in both structures, being more significant in the case of the underlap DMDG FinFET.