Post-bond Stack Testing for 3D Stacked IC

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• 作者：Surajit Kumar Roy (1) suraroy@gmail.com
  Dona Roy (1) mehulicalcutta@gmail.com
  Chandan Giri (1) chandangiri@gmail.com
  Hafizur Rahaman (1) rahaman_h@yahoo.co.in
• 关键词：SIC – ; DFT – ; Post ; bond testing
• 刊名：Lecture Notes in Computer Science
• 出版年：2012
• 出版时间：2012
• 年：2012
• 卷：7373
• 期：1
• 页码：59-68
• 全文大小：333.2 KB
• 参考文献：1. Iyengar, K.C., Marinissen, E.J.: Test Wrapper and Test Access Mechanism Co-optimization for System-on-chip. International Journal of Electronic Testing, Theory and Appilicatios 18, 213–230 (2002)
  2. Wu, X., Chen, Y., Chakrabarty, K., Xie, Y.: Test-access mechanism optimization for core-based three-dimensional SOCs. In: IEEE International Conference on Computer Design, pp. 212–218 (2008)
  3. Lee, H.S., Chakrabarty, K.: Test Challenges for 3DIntegrated Circuits. IEEE Design and Test of Computers 26, 26–35 (2009)
  4. Noia, B., Goel, S.K., Chakrabarty, K., Marinissen, E.J., Verbree, J.: Test Architecture Optimization for TSV-Based 3D Stacked ICs. In: IEEE Intl. Conf. on European Test Symposium, pp. 24–29 (2009)
  5. Marinissen, E.J., Verbree, J., Konijnenburg, M.: A Structured and Scalable Test Access Architecture for TSV-Based 3D Stacked ICs. In: IEEE Intl. Conf. VLSI Test Symposium, pp. 269–274 (2010)
  6. Noia, B., Chakrabarty, K., Marinissen, E.J.: Optimization Methods for Post-Bond Die-Internal/External Testing in 3D stacked ICs. In: IEEE Intl. Conf. Test Conference (ITC), pp. 1–9 (2010)
  7. Noia, B., Chakraborty, K., Goel, S.K., Marinissen, E.J., Verbree, J.: Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Transaction on Computer Aided Design of Integrated Circuit and System 30, 1705–1718 (2011)
  8. Bushnell, M.L., Agarawal, V.D.: Essentials of electronic testing. Springer Publishers
• 作者单位：1. Department of Information Technology, Bengal Engineering and Science University, Shibpur, India
• ISSN：1611-3349

文摘

In the embedded system design Through-silicon-via (TSV) based 3D stacked ICs (SICs) play an important role in semiconductor industry. But testing of these SICs are required during 3D assembly because different die stacking steps may introduce defects. In this paper, we address test architecture optimization for 3D stacked ICs implemented with hard die means where die-level test architecture is fixed. We consider two different SIC configurations and derive optimal solution to minimize overall test time when complete stack and multiple partial stacks, need to be tested. Results are performed for two handcrafted 3D SICs comprising of various SoCs from ITC’02 SoC test benchmarks. In this work we consider the test architecture optimization for 3D SIC where each die consists of one SoC. We present test schedules and corresponding test lengths for every multiple insertions and also show that total test lengths are decreased with the increasing number of test pins.