Wafer level high-density trench capacitors by using a two-step trench-filling process

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• 作者：Tao Zheng ; Gaowei Xu ; Le Luo
• 刊名：Microsystem Technologies
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：23
• 期：2
• 页码：399-404
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Electronics and Microelectronics, Instrumentation; Nanotechnology; Mechanical Engineering;
• 出版者：Springer Berlin Heidelberg
• ISSN：1432-1858
• 卷排序：23

文摘

This paper reports on the design, fabrication and electrical characterization of high-density SIS trench capacitors by using a two-step deposition process for fast-filling the deep trenches. LPCVD silicon nitride is employed as the dielectric material to provide high efficiency deposition in the high aspect ratio trenches. The capacitance density in trench capacitors with 25 nm thick Si₃N₄ is characterized as high as 57.8 nF/mm2, while the breakdown voltage in trench capacitors with 35 nm thick Si₃N₄ is recorded to be as high as 14.5 V. Furthermore, the capacitances are measured over an applied voltage range from −5 to 5 V, showing a small voltage-dependence of 1.2 and 0.6 % V−1 for the 25 and 35 nm thick Si₃N₄ trench capacitor, respectively. The leakage currents are measured and the current transport mechanisms are analyzed. The ESR and ESL of the capacitors with 25 and 35 nm thick Si₃N₄ are very small, as low as 35–65 mΩ and 0.2–0.28 pH for 0.04 mm2 electrode surface.