An Efficient Network-on-Chip Router for Dataflow Architecture
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- 作者：Xiao-Wei Shen ; Xiao-Chun Ye ; Xu Tan ; Da Wang…
- 关键词：multi ; destination ; router ; network ; on ; chip ; dataflow architecture ; high ; performance computing
- 刊名：Journal of Computer Science and Technology
- 出版年：2017
- 出版时间：January 2017
- 年：2017
- 卷：32
- 期：1
- 页码：11-25
- 全文大小：
- 刊物类别：Computer Science
- 刊物主题：Computer Science, general; Software Engineering; Theory of Computation; Data Structures, Cryptology and Information Theory; Artificial Intelligence (incl. Robotics); Information Systems Applications (
- 出版者：Springer US
- ISSN：1860-4749
- 卷排序：32
文摘
Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip (NoC). Thus the router design has a significant impact on the performance of dataflow architecture. Common routers are designed for control-flow multi-core architecture and we find they are not suitable for dataflow architecture. In this work, we analyze and extract the features of data transfers in NoCs of dataflow architecture: multiple destinations, high injection rate, and performance sensitive to delay. Based on the three features, we propose a novel and efficient NoC router for dataflow architecture. The proposed router supports multi-destination; thus it can transfer data with multiple destinations in a single transfer. Moreover, the router adopts output buffer to maximize throughput and adopts non-flit packets to minimize transfer delay. Experimental results show that the proposed router can improve the performance of dataflow architecture by 3.6x over a state-of-the-art router.