A 53mW IQ pipelined ADC for WLAN front end

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• 作者：Mao Ye (1)
  Bin Wu (1)
  Yong-xu Zhu (1)
  Dai Lan (2)
  Jianhua Jiang (1)
  Yumei Zhou (1)
  
• 关键词：WLAN ; Pipelined analog to digital converter ; Opamp sharing ; High speed reference buffer
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2014
• 出版时间：February 2014
• 年：2014
• 卷：78
• 期：2
• 页码：399-407
• 全文大小：1,270 KB
• 作者单位：Mao Ye (1)
  Bin Wu (1)
  Yong-xu Zhu (1)
  Dai Lan (2)
  Jianhua Jiang (1)
  Yumei Zhou (1)
  
  1. Institute of Microelectronics, Chinese Academy of Science, Beijing, China
  2. North China University of Technology, Beijing, China
  
• ISSN：1573-1979

文摘

This paper presents an analog to digital converter (ADC) architecture suitable for wideband wireless receiver system. The in-phase (I) and quadrature (Q) ADCs work independently, but share on-chip reference buffer and non-overlapped clock generation block for balance between two channels. The single ADC core consists of one front sample and hold amplifier, four cascade of 2.5 bit pipeline stages with pseudo-class AB opamp shared between adjacent stages and one 2 bit backend flash stage. The prototype was fabricated in standard 130?nm CMOS process and occupied silicon area of 0.62?mm2. Performance of 66?dB spurious-free-dynamic-range is measured at 80?MS/s with 1?Vpp input signal. The power dissipation of the whole chip is only 53?mW from a 1.1?V supply.