纳米SRAM寄生双极晶体管效应的仿真研究
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摘要
以65nm双阱CMOS(Complementary Metal Oxide Semiconductor)工艺的SRAM(Static Random Access Memory)为研究对象,采用三维数值模拟方法,结合SRAM中晶体管布局和邻近SRAM的相对位置,对寄生双极晶体管效应致纳米SRAM内部节点电势多次翻转的产生机制进行了深入阐述,对寄生双极晶体管效应致纳米SRAM发生MCU(Multiple Cell Upset)的影响因素进行了详细研究.发现寄生双极晶体管效应致SRAM内部节点电势多次翻转源于N阱中两个PMOS漏极电势的竞争过程,竞争过程与寄生双极晶体管效应的强弱相关,需综合考虑PMOS源极与N阱接触的距离、PMOS漏极与N阱的电势差两个因素.在纳米双阱CMOS工艺的SRAM中,PNP寄生双极晶体管效应对MCU起着重要作用.减小阱接触与SRAM单元的距离,可减弱邻近SRAM的寄生双极晶体管效应并降低MCU的发生概率,即使阱接触距离很近,特殊角度的斜入射和高LET(Linear Energy Transfer)值离子入射仍存在触发邻近SRAM的寄生双极晶体管效应并导致MCU的可能.
Considering the transistors distribution in a SRAMand the relative positions of two adjacent SRAMs,the mechanism of multiple upsets in 65 nm twin-well CMOS SRAMinternal nodes and the impact factors of multiple cell upset induced by parasitic bipolar effect are investigated through 3 D TCAD device simulation. It is found that multiple upsets in SRAMinternal nodes result from the competition of p+-drains in the n-well. The competition depends on the parasitic bipolar effect which is related to the distance between p+-source and n-well contact,as well as the electric potential difference between p+-drain and n-well. PNP parasitic bipolar transistors play an important role in nanometric twin-well CMOS SRAM. Although reducing the distance between SRAMand n-well contact can weaken parasitic bipolar effect,ions with special incident angles or high linear energy transfers can also trigger the parasitic bipolar effect in adjacent SRAMand induce multiple cell upset.
Considering the transistors distribution in a SRAMand the relative positions of two adjacent SRAMs,the mechanism of multiple upsets in 65 nm twin-well CMOS SRAMinternal nodes and the impact factors of multiple cell upset induced by parasitic bipolar effect are investigated through 3 D TCAD device simulation. It is found that multiple upsets in SRAMinternal nodes result from the competition of p+-drains in the n-well. The competition depends on the parasitic bipolar effect which is related to the distance between p+-source and n-well contact,as well as the electric potential difference between p+-drain and n-well. PNP parasitic bipolar transistors play an important role in nanometric twin-well CMOS SRAM. Although reducing the distance between SRAMand n-well contact can weaken parasitic bipolar effect,ions with special incident angles or high linear energy transfers can also trigger the parasitic bipolar effect in adjacent SRAMand induce multiple cell upset.
引文
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[8] Osada K,Yamaguchi K,Saitoh Y,et al. SRAM immunity to cosmic-ray-induced multi errors based on analysis of an induced parasitic bipolar effect[J]. IEEE J Solid-State Circuits,2004,39(5):827-833.
[9]Correas V,SaignéF,Sagnes B,et al. Prediction of multiple cell upset induced by heavy ions in a 90 nm bulk SRAM[J]. IEEE Trans Nucl Sci,2009,56(4):2050-2055.
[10] Olson B D,Ball D R,Warren K M,et al. Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design[J]. IEEE Trans Nucl Sci,2005,52(6):2132-2136.
[11]Slawosz U,Gilles G,Philippe R,et al. Single event upset and multiple cell upset modeling in commercial bulk 65-nm CM OS SRAM s and flip-flops[J]. IEEE Trans Nucl Sci,2010,57(4):1876-1883.
[12]Black J D,Ball II D R,Robinson W H,et al. Characterizing SRAM single event upset in terms of single and multiple node charge collection[J]. IEEE Trans Nucl Sci,2008,55(6):2943-2947.
[13]Giot D,Roche P,Gasiot G,et al. Heavy ion testing and 3-D simulations of multiple cell upset in 65nm standard SRAM s[J]. IEEE Trans Nucl Sci,2007,55(4):2048-2054.
[2] Maiz J,Hareland S,Zhang K,et al. Characterization of multi-bit soft error events in advanced SRAM s[A]. Proceedings of IEEE Int Electron Devices[C]. IEEE,2003.21. 4. 1-21. 4. 4.
[3] Ibe E,Taniguchi H,Yahagi Y,et al. Impact of scaling on neutron-induced soft error in SRAM s from a 250nm to a22nm design rule[J]. IEEE Trans Electron Devices,2010,57(7):1527-1538.
[4]Giot D,Roche P,Gasiot G,et al. Multiple bit upset analysis in 90nm SRAM s:Heavy ions testing and 3-D simulations[J]. IEEE Trans Nucl Sci,2007,54(4):904-911.
[5] Gnima T,Guillaume H,Karine C C,et al. Simulation of single and multi-node collection:impact on SEU occurrence in nanometric SRAM cells[J]. IEEE Trans Nucl Sci,2011,58(3):862-869.
[6]Zoutendyk J A,Schwartz H R,Nevill L R. Lateral charge transport from heavy-ion tracks in integrated circuits[J].IEEE Trans Nucl Sci,1988,35(6):1644-1647.
[7]Musseau O,Gardic F,Roche P,et al. Analysis of multiple bit upsets(M BU)in CM OS SRAM[J]. IEEE Trans Nucl Sci,1996,43(6):2879-2888.
[8] Osada K,Yamaguchi K,Saitoh Y,et al. SRAM immunity to cosmic-ray-induced multi errors based on analysis of an induced parasitic bipolar effect[J]. IEEE J Solid-State Circuits,2004,39(5):827-833.
[9]Correas V,SaignéF,Sagnes B,et al. Prediction of multiple cell upset induced by heavy ions in a 90 nm bulk SRAM[J]. IEEE Trans Nucl Sci,2009,56(4):2050-2055.
[10] Olson B D,Ball D R,Warren K M,et al. Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design[J]. IEEE Trans Nucl Sci,2005,52(6):2132-2136.
[11]Slawosz U,Gilles G,Philippe R,et al. Single event upset and multiple cell upset modeling in commercial bulk 65-nm CM OS SRAM s and flip-flops[J]. IEEE Trans Nucl Sci,2010,57(4):1876-1883.
[12]Black J D,Ball II D R,Robinson W H,et al. Characterizing SRAM single event upset in terms of single and multiple node charge collection[J]. IEEE Trans Nucl Sci,2008,55(6):2943-2947.
[13]Giot D,Roche P,Gasiot G,et al. Heavy ion testing and 3-D simulations of multiple cell upset in 65nm standard SRAM s[J]. IEEE Trans Nucl Sci,2007,55(4):2048-2054.