摘要
串行通信是上位机和硬件平台之间一种基本的数据交互方式,当硬件平台采用FPGA架构时,需要设计控制器来满足串口收发协议的需求。为了解决传统软核传送批量数据出现的丢包问题,设计的控制器软核定义了波特率时钟启动信号这一标志位,用以监控数据收发时的初始化使能是否有效。测试结果表明,所优化的IP逻辑软核可以实现批量数据的无误传输,提高了数据传输的高效性和准确性。
The serial communication is a basic way of data interaction between PC and hardware platform.When the hardware platform use FPGA architecture,it is necessary to design the controller to meet the needs of the serial transceiver protocol.In order to solve the problem of packet loss in batch data transmission by the traditional soft core,the designed controller in this paper defines the baud rate clock starting signal as a flag to monitor the validity of initialization enable when sending and receiving data.The test results show that the optimized IP logic soft core can realize the error-free transmission of batch data and improve the efficiency and accuracy of data transmission.
引文
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