工艺波动对纳米尺度MOS集成电路性能影响模型与相关方法研究
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摘要
随着半导体工艺的特征尺寸进入纳米数量级,日趋复杂的硅基MOS集成电路(Integrated Circuit IC)制造流程使得精确的工艺控制变得越来越困难,而芯片实际几何图形和纵向结构的不确定性导致器件的工作状态及其特性参数与设计目标产生显著偏离,产生工艺参数变化或工艺波动(Process Variation PV)现象。而且这一现象随着持续缩小的特征尺寸愈趋严重,使电路的性能和成品率受到极大影响。因此,工艺波动引起的可制造性(Design for manufacturability DFM)问题已成为纳米尺度IC设计和制造中亟待解决的技术瓶颈和重要挑战。
本文先探讨了IC制造中的内在波动源——随机掺杂波动(Random dopant Fluctuation RDF)及其概率密度分布,并用统计分析方法推导了RDF引起的阈值电压偏离标准差的简洁表达式,得到芯片上阈值电压的概率密度分布函数,该方法和得到的模型具有简洁和精确较高的特点。接着研究了RDF影响沟道载流子有效迁移率μeff以及电流增益因子β等参数的改变及其引起的电流失配,在详细研究失配模型的数学理论基础和已有模型特点基础上寻找并应用一个简单又有较高精度的改进ALPHA律平均漏电流模型,进而实现了65nm工艺的MOS电流失配解析模型。同时利用该模型,推导了既简单、有效又能保证精度的RDF引起的电流失配模型。
MOS电流的变化将影响模拟电路精度、功耗和带宽等各种性能和数字电路时序的偏差。因此本文实现了工艺波动RDF引起的用于模拟集成电路仿真分析的电路模型,并以基本电流镜为测试电路仿真验证,计算并得出电路在不同面积和偏置等设计条件下的性能参数关系表达式,并用于显示特定工艺波动下IC设计者选择器件面积和偏置条件对电路性能影响差异。再利用平均电流模型以CMOS反相器为测试电路,推导了数字电路时延及其变化标准差的解析模型,并用HSPICE的蒙特-卡罗仿真验证其精度和可靠性。
论文最后介绍了分析、设计、优化和控制IC工艺波动的相关数学和统计方法,主要包括σ空间分析法、主成分分析法和响应曲面法。并将统计实验设计(DOE)中的稳健设计方法与人工智能中的神经网络方法相结合,提出了数字逻辑函数的神经网络稳健设计方法,只要适当地扩展因子变量水平和取值,即有望用于1C工艺波动的优化设计中。
As feature size of semiconductor process is scaled to nano regime, silicon-based MOS integrated circuit (IC) manufacturing has become increasingly complex. This will make precise process control become increasingly difficult and result in the actual chip geometry, internal structure, working mechanism and characteristics parameters with a significant deviations from their design goals, which is called process parameters variation (PV) or process fluctuations. Furthermore, shrinking feature sizes with growing process variation makes the circuit performance degeneration and yield loss. So design for manufacturing (DFM) due to process variations has become a technical bottleneck and key challenge for today's nano-scale IC design and manufacturing.
Firstly, an internal source of variation called random dopant fluctuations (RDF) in IC manufacturing with its probability density function is discussed in this article. Then a statistical model of simple expression of threshold voltage standard deviation induced by RDF and its probability density distribution function of the chip is presented. This method and obtained model are both simple and accurate. After that, changes of effective channel carrier mobilityμeff and parameters such as current gain factor p and the standard deviation of current mismatch are studied cause by RDF. After study on the theoretical basis of mathematical models and characteristics of existing models in detail, a simple, high accuracy and improved average drain current model called ALPHA law is found and applied in the article, thus a MOS current mismatch analytical model is achieved for a 65 nm process. At the same time, a simple, effective and accurate current mismatch model induced by RDF is derived based on this model.
Variation of MOS current affects the accuracy, power, bandwidth and other performance of analog ICs and timing variability of digital ICs. A circuit simulation model for analog integrated circuits is presented considering PV due to RDF and an expression of different area and bias conditions of the circuit with a basic current mirror as a benchmark. The results show the impact on circuit performance for IC designers selecting different size and biasing condition in a specific process fluctuation. Average current model is reused to calculate standard deviation of an analytical model for digital circuit delay variability with a CMOS inverter as a benchmark, whose accuracy and reliability is verified by HSPICE Monte-Carlo simulations.
Finally mathematical and statistical methods in analysis, design, optimization and control of IC process fluctuations includingσspace analysis, principal component analysis and response surface methodology is introduced. Then a robust design method for digital logical function base on neural network is proposed after combination of robust design methods in statistical design of experimental (DOE) and artificial neural networks. As long as appropriate expansion levels and values of the variables of factors, it is expected to application to optimization for IC design in process variation.
本文先探讨了IC制造中的内在波动源——随机掺杂波动(Random dopant Fluctuation RDF)及其概率密度分布,并用统计分析方法推导了RDF引起的阈值电压偏离标准差的简洁表达式,得到芯片上阈值电压的概率密度分布函数,该方法和得到的模型具有简洁和精确较高的特点。接着研究了RDF影响沟道载流子有效迁移率μeff以及电流增益因子β等参数的改变及其引起的电流失配,在详细研究失配模型的数学理论基础和已有模型特点基础上寻找并应用一个简单又有较高精度的改进ALPHA律平均漏电流模型,进而实现了65nm工艺的MOS电流失配解析模型。同时利用该模型,推导了既简单、有效又能保证精度的RDF引起的电流失配模型。
MOS电流的变化将影响模拟电路精度、功耗和带宽等各种性能和数字电路时序的偏差。因此本文实现了工艺波动RDF引起的用于模拟集成电路仿真分析的电路模型,并以基本电流镜为测试电路仿真验证,计算并得出电路在不同面积和偏置等设计条件下的性能参数关系表达式,并用于显示特定工艺波动下IC设计者选择器件面积和偏置条件对电路性能影响差异。再利用平均电流模型以CMOS反相器为测试电路,推导了数字电路时延及其变化标准差的解析模型,并用HSPICE的蒙特-卡罗仿真验证其精度和可靠性。
论文最后介绍了分析、设计、优化和控制IC工艺波动的相关数学和统计方法,主要包括σ空间分析法、主成分分析法和响应曲面法。并将统计实验设计(DOE)中的稳健设计方法与人工智能中的神经网络方法相结合,提出了数字逻辑函数的神经网络稳健设计方法,只要适当地扩展因子变量水平和取值,即有望用于1C工艺波动的优化设计中。
As feature size of semiconductor process is scaled to nano regime, silicon-based MOS integrated circuit (IC) manufacturing has become increasingly complex. This will make precise process control become increasingly difficult and result in the actual chip geometry, internal structure, working mechanism and characteristics parameters with a significant deviations from their design goals, which is called process parameters variation (PV) or process fluctuations. Furthermore, shrinking feature sizes with growing process variation makes the circuit performance degeneration and yield loss. So design for manufacturing (DFM) due to process variations has become a technical bottleneck and key challenge for today's nano-scale IC design and manufacturing.
Firstly, an internal source of variation called random dopant fluctuations (RDF) in IC manufacturing with its probability density function is discussed in this article. Then a statistical model of simple expression of threshold voltage standard deviation induced by RDF and its probability density distribution function of the chip is presented. This method and obtained model are both simple and accurate. After that, changes of effective channel carrier mobilityμeff and parameters such as current gain factor p and the standard deviation of current mismatch are studied cause by RDF. After study on the theoretical basis of mathematical models and characteristics of existing models in detail, a simple, high accuracy and improved average drain current model called ALPHA law is found and applied in the article, thus a MOS current mismatch analytical model is achieved for a 65 nm process. At the same time, a simple, effective and accurate current mismatch model induced by RDF is derived based on this model.
Variation of MOS current affects the accuracy, power, bandwidth and other performance of analog ICs and timing variability of digital ICs. A circuit simulation model for analog integrated circuits is presented considering PV due to RDF and an expression of different area and bias conditions of the circuit with a basic current mirror as a benchmark. The results show the impact on circuit performance for IC designers selecting different size and biasing condition in a specific process fluctuation. Average current model is reused to calculate standard deviation of an analytical model for digital circuit delay variability with a CMOS inverter as a benchmark, whose accuracy and reliability is verified by HSPICE Monte-Carlo simulations.
Finally mathematical and statistical methods in analysis, design, optimization and control of IC process fluctuations includingσspace analysis, principal component analysis and response surface methodology is introduced. Then a robust design method for digital logical function base on neural network is proposed after combination of robust design methods in statistical design of experimental (DOE) and artificial neural networks. As long as appropriate expansion levels and values of the variables of factors, it is expected to application to optimization for IC design in process variation.
引文
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