低功耗软件优化技术研究
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摘要
现代计算机系统中功耗成为越来越重要的问题,主要体现在以下两个方面:1)对于嵌入式设备来说,往往依靠电池供电,受到有限的电池供电时间的制约,功耗成为除了性能和面积之外的另一个重要系统参数。与半导体技术的发展速度相比,电池技术发展缓慢,未来的移动设备必须在有限的能量供应下发挥更大的效能。2)对于高性能计算机系统来说,为了提高处理器的性能,晶体管的集成度越来越高,导致功耗急剧地增长。而功耗的急剧增长进一步提高了芯片的封装和制冷成本,且高温环境下的执行增加了芯片的失效率,导致计算机系统的可靠性下降。对大规模并行计算机系统来说,过高的功耗更是造成了巨大的能量消耗。尽管多核处理器的发展在一定程度上缓解了性能和功耗之间的矛盾,但也必须看到多核处理器存在发热大、散热难等问题。
从底层的电路技术,到逻辑技术、体系结构技术和高层的软件技术,出现了各种用于降低计算机系统功耗的方法。本文的研究重点在于软件的低功耗技术,结合传统的面向性能的优化方法,通过动态电压调节和部件关闭等技术来降低功耗,并同时兼顾了需满足的性能要求。具体说来,本文的主要工作包括以下几个方面:(1)对几种处理器低功耗技术进行了分析,并同时分析了片上存储系统的功耗特征;(2)研究了处理器和存储器协调的能量优化方法,从能量最优化和能量受限条件下的性能最优化两个方面进行了研究;(3)研究了低功耗的软件预取优化方法,结合静态电压调节和动态电压调节方法展开了研究;(4)研究了面向多核结构的并行程序能量优化方法,将处理器核关闭技术和动态电压调节技术有效地应用在面向多核结构的并行程序能量优化中。本文的主要创新如下:
1、提出了能量最优的面向微处理器和存储器的能量优化模型。弥补了过去只考虑性能优化、不考虑能量优化的不足。该模型建模了软件预取优化中出现的各种情况,通过同时调节处理器和存储器的电压和频率,在满足一定性能约束条件下最小化系统的能量消耗。
2、提出了能量受限的面向微处理器和存储器的能量优化模型。解决了有限能量供给条件下的性能优化问题。该模型建模了软件预取优化中出现的各种情况,通过同时调节处理器和存储器的电压和频率,在满足一定能量约束条件下最优化系统的性能目标。
3、提出了基于静态电压调节的低功耗软件预取优化方法。该方法一方面通过调节处理器的电压来降低功耗,另一方面通过调整预取距离来获得性能和功耗的进一步改善,最终使程序运行的平均功耗不超过预取优化前的功耗,消除了因软件预取造成的功耗明显增加,且获得了有效的性能提高。
4、提出了基于动态电压调节的功耗指导的软件预取优化算法PDP-DVS。该算法通过实时监控系统的功耗水平,自适应地调节处理器的电压值,保证程序消耗的平均功耗不超过未预取时的值,同时获得有效的性能改进。模拟实验结果表明,算法PDP-DVS可以保证在功耗不增加的前提下,获得有效的性能提高。
5、提出了面向多核结构的并行程序能量优化方法。该方法一方面通过处理器核关闭技术调整程序在执行串行部分时的处理器核数目;另一方面通过动态电压调节技术调节程序在执行并行部分时的每个处理器核的电压和频率值。模拟结果显示该方法可以有效降低并行程序的能量消耗。
Power Consumption has become a more and more important problem in current computer system, especially for processors. The major reasons are: 1) For embedded devices, they are powered by the battery. Constrained by the limited battery life time, power dissipation becomes another important system parameter besides performance and area. Compared with the speed of semiconductor technology development, the speed of the battery technology development is much lower. So it is significant for the futural battery-powered mobile devices to have better energy efficiency supplied with the limited energy consumption. 2) For high performance computer systems, in order to achieve higher performance, more and more transistors are integrated, which sharply increases the power dissipation. While rapid power increase further adds the chip packaging and cooling cost. In addition, the higher temperature increases the probability of the invalidation in integrated circuits (ICs) and leads to the decrease of the system reliability. For large-scale parallel systems, high power consumption consumes the huge energy resource. Although the progress of multi-core processors partly alleviates the conflict between the performance and power, multi-core processors will bring about the large heat and cooling problem. From the study for low power in recent years, multi-core based software low-power research has become the focus.
A large number of novel low-power techniques at different levels including circuit, logic, architecture and software levels have been proposed to reduce power and energy. This thesis aims at study of low-power software optimization technology. Based on traditional performance-oriented optimization, we use dynamic voltage scheduling and shutting down technology to reduce power consumption while meeting the performance demand. In details, the major work consists of the following aspects: (1) Analyzing several low-power techniques and the power characteristics of on-chip memory; (2) Studying the enegy optimization method combining the processor with main memory. Two problems are considered: one is energy optimization with performance constraint and the other is energy-constrained performance optimization; (3) Studying low-power software prefetching optimization method, which combines static voltage scheduling with dynamic voltage scheduling; (4) Studying multi-core based energy optimization method for parallel programs. This method effectively applies shutting down technique and dynamic voltage scheduling on multi-core based energy optimization for parallel programs. The main contributions of this thesis are as follows:
1. Proposing an energy-optimal energy optimization model based on processor and main memory, which remedies the deficiency that optimizes only the performance but the energy consumption. This model describes all kinds of situations appearing in the software prefetching. This model minimizes the energy consumption of the system by simultaneously adjusting processor's voltage and frequency and main memory's voltage and frequency.
2. Proposing an energy-constrained energy model based on processor and mainmemory, which resolves the performance optimization under the limited energy supply. This model describes all kinds of situations appearing in the software prefetching. This model minimizes the execution time of the system within a limited energy constraint by simultaneously adjusting processor's voltage and frequency and main memory's voltage and frequency.
3. Proposing static voltage scheduling based low-power software prefetching method.One side this method reduces the power dissipation by adjusting the voltage, and on the other side it achieves the further performance and power improvement by adjusting the prefetch distance. At last the average power dissipation of the whole program is no more than when no prefetch. That is, this method can improve the performance while eliminating the power increase due to software prefetching.
4. Proposing dynamic voltage scheduling based low-power software prefetchingalgorithm PDP-DVS. This algorithm adjusts the processor's voltage level and guarantees the average power dissipation under the level when no prefetch by on-time monitoring the power of the system. Simulation results show that PDP-DVS can achieve the effective performance improvement without the power increase.
5. Proposing the multi-core based energy optimization method for parallel programs.One hand this method uses shutting down technology to adjust the number of processors during the serial program execution, and on the other hand it uses dynamic voltage scheduling to adjust the voltage and frequency of each processor during the parallel program execution. Simulation results show this method can effectively reduce the energy consumption of parallel programs.
从底层的电路技术,到逻辑技术、体系结构技术和高层的软件技术,出现了各种用于降低计算机系统功耗的方法。本文的研究重点在于软件的低功耗技术,结合传统的面向性能的优化方法,通过动态电压调节和部件关闭等技术来降低功耗,并同时兼顾了需满足的性能要求。具体说来,本文的主要工作包括以下几个方面:(1)对几种处理器低功耗技术进行了分析,并同时分析了片上存储系统的功耗特征;(2)研究了处理器和存储器协调的能量优化方法,从能量最优化和能量受限条件下的性能最优化两个方面进行了研究;(3)研究了低功耗的软件预取优化方法,结合静态电压调节和动态电压调节方法展开了研究;(4)研究了面向多核结构的并行程序能量优化方法,将处理器核关闭技术和动态电压调节技术有效地应用在面向多核结构的并行程序能量优化中。本文的主要创新如下:
1、提出了能量最优的面向微处理器和存储器的能量优化模型。弥补了过去只考虑性能优化、不考虑能量优化的不足。该模型建模了软件预取优化中出现的各种情况,通过同时调节处理器和存储器的电压和频率,在满足一定性能约束条件下最小化系统的能量消耗。
2、提出了能量受限的面向微处理器和存储器的能量优化模型。解决了有限能量供给条件下的性能优化问题。该模型建模了软件预取优化中出现的各种情况,通过同时调节处理器和存储器的电压和频率,在满足一定能量约束条件下最优化系统的性能目标。
3、提出了基于静态电压调节的低功耗软件预取优化方法。该方法一方面通过调节处理器的电压来降低功耗,另一方面通过调整预取距离来获得性能和功耗的进一步改善,最终使程序运行的平均功耗不超过预取优化前的功耗,消除了因软件预取造成的功耗明显增加,且获得了有效的性能提高。
4、提出了基于动态电压调节的功耗指导的软件预取优化算法PDP-DVS。该算法通过实时监控系统的功耗水平,自适应地调节处理器的电压值,保证程序消耗的平均功耗不超过未预取时的值,同时获得有效的性能改进。模拟实验结果表明,算法PDP-DVS可以保证在功耗不增加的前提下,获得有效的性能提高。
5、提出了面向多核结构的并行程序能量优化方法。该方法一方面通过处理器核关闭技术调整程序在执行串行部分时的处理器核数目;另一方面通过动态电压调节技术调节程序在执行并行部分时的每个处理器核的电压和频率值。模拟结果显示该方法可以有效降低并行程序的能量消耗。
Power Consumption has become a more and more important problem in current computer system, especially for processors. The major reasons are: 1) For embedded devices, they are powered by the battery. Constrained by the limited battery life time, power dissipation becomes another important system parameter besides performance and area. Compared with the speed of semiconductor technology development, the speed of the battery technology development is much lower. So it is significant for the futural battery-powered mobile devices to have better energy efficiency supplied with the limited energy consumption. 2) For high performance computer systems, in order to achieve higher performance, more and more transistors are integrated, which sharply increases the power dissipation. While rapid power increase further adds the chip packaging and cooling cost. In addition, the higher temperature increases the probability of the invalidation in integrated circuits (ICs) and leads to the decrease of the system reliability. For large-scale parallel systems, high power consumption consumes the huge energy resource. Although the progress of multi-core processors partly alleviates the conflict between the performance and power, multi-core processors will bring about the large heat and cooling problem. From the study for low power in recent years, multi-core based software low-power research has become the focus.
A large number of novel low-power techniques at different levels including circuit, logic, architecture and software levels have been proposed to reduce power and energy. This thesis aims at study of low-power software optimization technology. Based on traditional performance-oriented optimization, we use dynamic voltage scheduling and shutting down technology to reduce power consumption while meeting the performance demand. In details, the major work consists of the following aspects: (1) Analyzing several low-power techniques and the power characteristics of on-chip memory; (2) Studying the enegy optimization method combining the processor with main memory. Two problems are considered: one is energy optimization with performance constraint and the other is energy-constrained performance optimization; (3) Studying low-power software prefetching optimization method, which combines static voltage scheduling with dynamic voltage scheduling; (4) Studying multi-core based energy optimization method for parallel programs. This method effectively applies shutting down technique and dynamic voltage scheduling on multi-core based energy optimization for parallel programs. The main contributions of this thesis are as follows:
1. Proposing an energy-optimal energy optimization model based on processor and main memory, which remedies the deficiency that optimizes only the performance but the energy consumption. This model describes all kinds of situations appearing in the software prefetching. This model minimizes the energy consumption of the system by simultaneously adjusting processor's voltage and frequency and main memory's voltage and frequency.
2. Proposing an energy-constrained energy model based on processor and mainmemory, which resolves the performance optimization under the limited energy supply. This model describes all kinds of situations appearing in the software prefetching. This model minimizes the execution time of the system within a limited energy constraint by simultaneously adjusting processor's voltage and frequency and main memory's voltage and frequency.
3. Proposing static voltage scheduling based low-power software prefetching method.One side this method reduces the power dissipation by adjusting the voltage, and on the other side it achieves the further performance and power improvement by adjusting the prefetch distance. At last the average power dissipation of the whole program is no more than when no prefetch. That is, this method can improve the performance while eliminating the power increase due to software prefetching.
4. Proposing dynamic voltage scheduling based low-power software prefetchingalgorithm PDP-DVS. This algorithm adjusts the processor's voltage level and guarantees the average power dissipation under the level when no prefetch by on-time monitoring the power of the system. Simulation results show that PDP-DVS can achieve the effective performance improvement without the power increase.
5. Proposing the multi-core based energy optimization method for parallel programs.One hand this method uses shutting down technology to adjust the number of processors during the serial program execution, and on the other hand it uses dynamic voltage scheduling to adjust the voltage and frequency of each processor during the parallel program execution. Simulation results show this method can effectively reduce the energy consumption of parallel programs.
引文
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