MPEG-2解码芯片中AMBA总线、DMA控制器和UART接口的设计
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摘要
目前,数字电视日益成为人们关注的焦点,而限制其发展的一个主要因素是没有一种适合数字电视广播系统的视频压缩编码算法和传输标准。随着研究的一步步深入,“活动图像专家组”(MPEG, Moving Picture Experts Group)于1993年提出了MPEG-2压缩编码标准,该标准对数字电视的发展起到了决定性推动作用。
本文采用Top-Down方法,首先分析了MPEG-2解码芯片的设计要求和整体结构,并在这个背景下,采用Verilog硬件描述语言完成了AMBA总线,DMA控制器和UART接口三个模块的RTL代码,使之符合这个SOC架构。然后,利用Modelsim软件,对上述三个模块进行功能验证和设计优化,同时在测试激励程序(testbench)中加入systemverilog的断言语法,方便在模拟时能够及时捕捉错误,并且迅速准确的定位错误所在,大大简化了纠错工作。最后,使用QuartusⅡ的Mega Wizard插件管理器定制单端口的ROM和SRAM IP核,编写带有AHB接口的ROM控制器和带有APB接口的SRAM控制器,并且将其和上述三个模块集成整合,搭建相应的FPGA平台,同时嵌入Minimips使之成为一个最小系统,借助软件组提供的Firmware,对AMBA总线、DMA控制器和UART接口进行软硬件协同验证。
在经过充分的功能仿真,FPGA验证和软硬件协同验证后,MPEG-2解码芯片采用SMIC 0.13um工艺库进行流片测试,目前这三个模块工作性能良好。本文的实验结果表明AMBA总线,DMA控制器,UART接口在27MHz、108MHz、150MHz频率下都可以正常工作,能够满足数字电视标清和高清两种标准。
At present, digital TV is increasingly becoming the focus of attention. However, for a long time, a major factor to restrict digital TV development is that there is not a video compression coding and transmission standard suitable for television broadcasting system. With the step-by-step in-depth understanding "Moving Picture Experts Group" (MPEG) proposed MPEG-2 compressing standard in 1993, which has played a decisive role in promoting the development of digital television.
In this paper, Top-Down design methodology is used. First of all, analysis the design requirement and overall structure of MPEG-2 Decoder chip, and against this background, complete the RTL code of the AMBA bus, DMA controller and UART interface modules by using Verilog Hardware Description Language, and make them compatible with the SOC framework. Then, complete the function verification of the above-mentioned three modules by Modelsim software. At the same time, add assert syntax in the testbench, which can catch errors in time conveniently when imitating, and prompt accurate positioning error that facilitated the error correction job greatly. Finally, custom single-port ROM and SRAM core by Mega Wizard plug-in manager tool, and integrate them with the above-mentioned three modules and MINIMIPS to build FPGA for co-verification.
After the full function simulation, FPGA verification, hardware and software co-verification, MPEG-2 decoder chip taped out using SMIC 0.13um process tape library, and the current performance of the three modules work well. In this paper, the results show that the design of AMBA bus, DMA controller and UART interface can operate at 27MHz,108MHz, 150MHz, which meets the SDTV and HDTV standard.
本文采用Top-Down方法,首先分析了MPEG-2解码芯片的设计要求和整体结构,并在这个背景下,采用Verilog硬件描述语言完成了AMBA总线,DMA控制器和UART接口三个模块的RTL代码,使之符合这个SOC架构。然后,利用Modelsim软件,对上述三个模块进行功能验证和设计优化,同时在测试激励程序(testbench)中加入systemverilog的断言语法,方便在模拟时能够及时捕捉错误,并且迅速准确的定位错误所在,大大简化了纠错工作。最后,使用QuartusⅡ的Mega Wizard插件管理器定制单端口的ROM和SRAM IP核,编写带有AHB接口的ROM控制器和带有APB接口的SRAM控制器,并且将其和上述三个模块集成整合,搭建相应的FPGA平台,同时嵌入Minimips使之成为一个最小系统,借助软件组提供的Firmware,对AMBA总线、DMA控制器和UART接口进行软硬件协同验证。
在经过充分的功能仿真,FPGA验证和软硬件协同验证后,MPEG-2解码芯片采用SMIC 0.13um工艺库进行流片测试,目前这三个模块工作性能良好。本文的实验结果表明AMBA总线,DMA控制器,UART接口在27MHz、108MHz、150MHz频率下都可以正常工作,能够满足数字电视标清和高清两种标准。
At present, digital TV is increasingly becoming the focus of attention. However, for a long time, a major factor to restrict digital TV development is that there is not a video compression coding and transmission standard suitable for television broadcasting system. With the step-by-step in-depth understanding "Moving Picture Experts Group" (MPEG) proposed MPEG-2 compressing standard in 1993, which has played a decisive role in promoting the development of digital television.
In this paper, Top-Down design methodology is used. First of all, analysis the design requirement and overall structure of MPEG-2 Decoder chip, and against this background, complete the RTL code of the AMBA bus, DMA controller and UART interface modules by using Verilog Hardware Description Language, and make them compatible with the SOC framework. Then, complete the function verification of the above-mentioned three modules by Modelsim software. At the same time, add assert syntax in the testbench, which can catch errors in time conveniently when imitating, and prompt accurate positioning error that facilitated the error correction job greatly. Finally, custom single-port ROM and SRAM core by Mega Wizard plug-in manager tool, and integrate them with the above-mentioned three modules and MINIMIPS to build FPGA for co-verification.
After the full function simulation, FPGA verification, hardware and software co-verification, MPEG-2 decoder chip taped out using SMIC 0.13um process tape library, and the current performance of the three modules work well. In this paper, the results show that the design of AMBA bus, DMA controller and UART interface can operate at 27MHz,108MHz, 150MHz, which meets the SDTV and HDTV standard.
引文
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[17]易志强.有线数字电视SoC芯片软硬件协同设计及其片上总线研究[D].浙江：浙江大学,2006：1-3
[18]周岩.MPEG-2解码器运动补偿ASIC设计[D].上海：同济大学,2005：1-4
[19]张立超.数字电视信源解码系统架构设计与总线分析[D].北京：北京工业大学,2008：1-4
[20]吴智华,罗嵘,杨华中.一种用于MPEG-2解码芯片的高效内存存储结构[J].微电子学,2007,37(6)：878-886
[21]何铁军.数字视频技术在智能运输系统中的应用研究[D].南京：东南大学,2004：4,9-10
[22]徐洄.高速公路MPEG2/4网络视频编解码器研究与设计[D].吉林：吉林大学,2007：15-20
[23]Cordan, B. An Efficient Bus Architecture for System-on-Chip Design [J]. Proceedings of the IEEE 1999, Custom Integrated Circuits,1999,28(2):623-626
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[26]朱嘉.基于AMBA总线结构的高性能存储接口的研究与设计[D].上海：同济大学,2007：6-9
[27]刘俊江.基于ARM核的AHB_USB2.0接口ASIC设计[D].成都：电子科技大学,2007：11-18
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[36]William Stallings张昆藏,施一萍,经致远译.计算机组成与结构-性能设计[M].北京：清华大学出版社,2001：135-149
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[38]吕林清.微型计算机原理与接口技术[M].北京：科学出版社,2005：137-150,198-200
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[40]陈玉梅.面向SOC的UART及DMA控制器IP软核的设计[D].山东：山东大学,2007：5-9,17-18
[41]谢琅,杨艳.基于AMBA总线的DMA控制器IP核设计与分析[J].计算机应用研究,2006,23(12)：213-214
[42]O'Nils M, Jantsch A. Synthesis of DMA controllers from architecture independent descriptions of HW/SW communication protocols[C]. Proceedings.Twelfth International Conference On VLSI Design,1999:138-145
[43]Shi Xinlei, Yang Jun, Lu Shengli. The Design and Optimization of DMA Controller in Embedded System-on-a-Chip [J]. Electronic Engineer,2004,30(1):5
[44]Chia-Hao Yu, Chung-Kai Liu, Chih-Heng Kang, Tsun-Hsien Wang, Chih-Chien Shen, Shau-Yin Tseng. An Efficient DMA Controller for Multimedia Application in MPU Based SOC[C]. IEEE International Conference on Multimedia and Expo,2007:80-83
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