高清晰度电视中均衡器的设计及其芯片实现
摘要
高清晰度电视(HDTV)技术是当今世界上最先进的图象压缩编码技术和数字通信技术的结合，是当今世界高技术竞争的焦点之一，掌握了这一技术就可能抢占到未来电子技术的制高点，控制新一代电子产品的市场，抢占商机。
均衡器在HDTV的接收机中是非常重要的一部分，因为均衡器的作用是消除码间干扰，码间干扰消除得是否彻底，对接收机的整体性能起着举足轻重的意义。
本文探讨了HDTV地面残留边带调制(VSB)系统和DVB系统的电缆标准中均衡器的结构与算法，讨论了他们的异同点以及给出了芯片实现方案。
本文第一章首先介绍了HDTV的发展史；接着从系统上介绍了HDTV的VSB和DVB的电缆标准。
第二章介绍了均衡器的基本原理。
第三章给出实际实现的VSB和DVB电缆标准中均衡器的算法和结构，分析比较其异同点，并给出C语言仿真性能比较曲线。
第四章给出ASIC设计的规范和流程，以及最近流行的SOC设计方法学。接着介绍了深亚微米工艺下ASIC设计面临的挑战以及解决方法。
第五章给出均衡器在ASIC实现过程中碰到的问题以及解决方法。针对均衡器芯片实现的特殊性，我们从硬件结构划分开始，然后给出一种应用于均衡器芯片实现中的滤波器IP化方法；在经过对快速乘法器结构的研究后，提出一种在速度和面积上都比较优异的乘法器结构应用于滤波器的乘法中；在综合的时候使用基于datapath的综合技术，最后给出两种使用的验证技术。
本文的主要贡献在于通过对上述两种标准均衡器方案的比较和总结，通过芯片实现的例子，希望能够对以后做出基于我国自己标准的均衡器能起到抛砖引玉的作用。
HDTV (high definition television) technology integrates the most advanced image compressed encoding technology and the digital communication technology; it has become one of the focuses in the high-tech competitions. Having the imitative in this field will take the lead of high technology in the future, and get great chance in the growing market.
Equalizer takes an important role in HDTV receiver; its effect on reducing ISI (InterSymbol Interference) holds the balance of performance of the whole receiver. In this paper, structure and algorithm of the equalizer used in cable standard of HDTV VSB (Vestigial Sideband) system and DVB (Digital Video Broadcasting) system are analyzed, and similarities and differences are given in algorithm and ASIC implementation in VSB system is given.
In chapter one, the history of HDTV is introduced followed by VSB scheme and DVB scheme.
In chapter two, the principle of equalizer is introduced.
In chapter three, structure and algorithm of the equalizer used in VSB and DVB are exhibited, and similarities and differences are given, then performance comparison curve is given.
In chapter four, we discuss the criterion and design flow of a whole ASIC design and SOC design methodology. Chanllanges and solutions are given in VDSM design.
In chapter five, we discuss the implementation of equalizer in the receiver ASIC. The particularities are given such as IP core technology, fast multiplier, and datapath synthesis technology. Then we introduce two verification methods.
The most contribution of my paper is to throw out a brick to attract a jade: to design equalizer based on our own national standard will benefit from my comparisons and examples.
均衡器在HDTV的接收机中是非常重要的一部分，因为均衡器的作用是消除码间干扰，码间干扰消除得是否彻底，对接收机的整体性能起着举足轻重的意义。
本文探讨了HDTV地面残留边带调制(VSB)系统和DVB系统的电缆标准中均衡器的结构与算法，讨论了他们的异同点以及给出了芯片实现方案。
本文第一章首先介绍了HDTV的发展史；接着从系统上介绍了HDTV的VSB和DVB的电缆标准。
第二章介绍了均衡器的基本原理。
第三章给出实际实现的VSB和DVB电缆标准中均衡器的算法和结构，分析比较其异同点，并给出C语言仿真性能比较曲线。
第四章给出ASIC设计的规范和流程，以及最近流行的SOC设计方法学。接着介绍了深亚微米工艺下ASIC设计面临的挑战以及解决方法。
第五章给出均衡器在ASIC实现过程中碰到的问题以及解决方法。针对均衡器芯片实现的特殊性，我们从硬件结构划分开始，然后给出一种应用于均衡器芯片实现中的滤波器IP化方法；在经过对快速乘法器结构的研究后，提出一种在速度和面积上都比较优异的乘法器结构应用于滤波器的乘法中；在综合的时候使用基于datapath的综合技术，最后给出两种使用的验证技术。
本文的主要贡献在于通过对上述两种标准均衡器方案的比较和总结，通过芯片实现的例子，希望能够对以后做出基于我国自己标准的均衡器能起到抛砖引玉的作用。
HDTV (high definition television) technology integrates the most advanced image compressed encoding technology and the digital communication technology; it has become one of the focuses in the high-tech competitions. Having the imitative in this field will take the lead of high technology in the future, and get great chance in the growing market.
Equalizer takes an important role in HDTV receiver; its effect on reducing ISI (InterSymbol Interference) holds the balance of performance of the whole receiver. In this paper, structure and algorithm of the equalizer used in cable standard of HDTV VSB (Vestigial Sideband) system and DVB (Digital Video Broadcasting) system are analyzed, and similarities and differences are given in algorithm and ASIC implementation in VSB system is given.
In chapter one, the history of HDTV is introduced followed by VSB scheme and DVB scheme.
In chapter two, the principle of equalizer is introduced.
In chapter three, structure and algorithm of the equalizer used in VSB and DVB are exhibited, and similarities and differences are given, then performance comparison curve is given.
In chapter four, we discuss the criterion and design flow of a whole ASIC design and SOC design methodology. Chanllanges and solutions are given in VDSM design.
In chapter five, we discuss the implementation of equalizer in the receiver ASIC. The particularities are given such as IP core technology, fast multiplier, and datapath synthesis technology. Then we introduce two verification methods.
The most contribution of my paper is to throw out a brick to attract a jade: to design equalizer based on our own national standard will benefit from my comparisons and examples.
引文
[1] Guide to the Use of the ATSC Digital Television Standard, Doc A/54, 4 Oct. 1995
[2] "ATSC Digital Television Standard", ATSC Standard A/53, September 16, 1995
[4] “数字电视的进展以及对中国发展数字电视的建议”，徐孟侠，《电视技术》2001年第4期，pp4～11
[5] Advance Digital High Definition System Desrition, David Sarnoff Reserch Center and Philips Laboratories, Jan. 1992
[6] Channel Compatible Digicipjer HDTV System, Submitted by Massachsetts Institute of Technology, on Bahalf of the American Television Alliance, 14, May 1992
[7] 马长华，“八五”期间HDTV科研取得显著成果，广播与电视技术，1996年第6期
[8] 马长华，中国数字化电视广播发展道路，1997-03-20
[9] Special issue on HDTV broadcasting, IEEE Trans. roadcasting, Vol. 37, no.4, pp.121-172, Dec. 1992.
[10] Digicipher HDTV System Description, General Instument Corporation Video Division, Aug.22 1991
[11] ETSI, EN 300 429, Digital Video Broadcasting (DVB): Framing structure, channel coding and modulation for cable systems V1.2.1 (1998-04)
[1] 姚庆栋，梁慧君，戴文琪，《数字无线传输》，浙江大学出版社，1992
[2] R. W. Lucky, J. Salz, and E. J. Weldon, Jr. "Principles of data communication", New York, McGraw-Hill, 1968
[3] 李乐民，叶化祥，《数字传输设备中的均衡器》，人民邮电出版社，1980
[4] S. U. H. Qreshi, "Adaptive Equalization", Proc. IEEE, vol. 3, No. 9, pp.1349-1387, 1985
[5] B. Widrow and M. Hoff, Jr., "Adaptive switching circuits", IRE WESCON Com. Rec. PT4, pp.96-104, 1960
[6] 姚彦等，《数字微波中继通信工程》，人民邮电出版社，1990
[7] 陈尚勤，李晓峰，《快速自适应信息处理》，人民邮电出版社，1993
[8] S. U. H. Qreshi, "Fast start-up equalization with periodic training sequence", IEEE Trans. Inform. Theory, vol. IT-23, pp. 553-563, Sept. 1977.
[9] R. D. Gitlin and S. B. Weistein, "On the required tap-weight precision for digital-implemented adaptive mean square equalizers", B.S.T.J., vol. 58, no. 2, pp. 503-321, Feb. 1979
[10] S. A. Altedar and N.C.Beaulieu, "Upper bounds to the error probability of decision feedback equalization", IEEE Trans. Inform. Theory, vol. 39, no. 1, pp. 145-156, Jan. 1993
[11] 郭梯云等，《数据传输》，人民邮电出版社，1993
[1] Adaptive Equalization, U. H. Qureshi, proceedings of the IEEE, Vol. 73, No. 9, Sep. 1985, pp1349～1387
[2] 《数字无线传输》，姚庆栋，梁慧君，戴文琪，浙江大学出版社，1992年
[3] 陈叔远，颜绍书编著，《相移均衡器》，人民邮电出版社，1984
[4] Self-Recovering Algorithm for Multilevel System, Y. Sato, IEEE Transactions on Communications, June 1975, pp679～682
[5] Blind Equalizers, A. Benveniste, M. Goursat, IEEE Transactions on Communications, Vol. COM-32, No. 8, Aug. 1984, pp871～883
[6] Fast Recovery Equalization Techniques for DTV Signals, N. Deshpande, IEEE Transactions on Broadcasting, Vol. 43, No. 4, Dec. 1997, pp370～377
[7] New Criteria for Blind Deconvolution on Nonminimum Phase Systems (Channels), O. Shalvi, E. Weinstin, IEEE Transactions on Information Theory, Vol. 36, No. 2, March 1990, pp312～321
[8] Admissibility in Blind Adaptive Channel Equalization, C. R. Johnson, IEEE Control Systems, January 1991, pp3～pp15
[9] Adaptive Blind Equalization Coupled With Carrier Recovery for HDTV Modem, Y. S. Choi, H.1 Hwarg, D. I. Song, IEEE Transactions on Consumer Electronics, Vol. 39, No. 3, Aug. 1993, pp384～391
[10] 吴禀圣，HDTV接收系统中的均衡器的设计，浙江大学硕士学位论文，2002
[11] 陈慧芳，HFC网络数字传输技术研究——上行和MAC层研究，浙江大学博士学位论文，2000
[1] 张明，《Verilog HDL实用教程》，电子科技大学出版社，1999．11
[2] Henry Chang, Larry Cooke, Merrill Hunt etc. Surviving the SOC Revolution: a guide to platform-based design. USA: KLUWER Academic Publishers. 1999.31～32.
[3] Petlin, O.; Genusov, A.; Wakeman, L. Methodology and code reuse in the verification of telecommunication SOCs. ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000. Page(s): 187-191.
[4] 韩泽耀，高性能FFT处理器的VLSI实现，浙江大学博士学位论文，2002
[5] 黄国勇，基于IP的SOC设计，世界电子元器件，2001．9
[6] Synopsys MiniDAC 2001, Beijing
[7] 魏少军，SOC设计方法学(一)、(二)，电子产品世界，2001．5
[8] 张纯蓓，IP、SOC与设计技术(一)、(二)，电子产品世界，1999．12
[1] ATSC Standard A/53-1995, ATSC Digital Television Standard.
[2] Qureshi S.U.,Adaptive Equalization, Proc. IEEE, 1985, 73. 1349-1387
[3] 兰景宏，吉利久，IP的复用设计，世界产品与技术，2000，3：8-10
[4] 罗义军，张朝阳，仇佩亮，一种新颖的横向滤波器的优化结构，电路与系统学报，2000，3：22—25
[5] Han, T. and K.A. Carlson. 1987. Fast area-efficient VSLI adders. In: Proceedings, 8th IEEESymposium on Computer Arithmetic, pp 49～56.
[6] Ling, H. 1981. Hign-speed binary adder. IBM Journal of Research and Development, vol.
[7] M. D. Ercegovac and T. Lang, "On-the-fly conversion of redundant into conventional representations," IEEE Trans. on Computer, vol. C-36, no. 7, pp. 895-897, July 1987
[8] M. D. Ercegovac and T. Lang, "Fast multiplication without carry-propagate addition," IEEE Trans. on Computers, vol. C-39, pp. 1385-1390, Nov. 1990
[9] L. Ciminiera and P. Montuschi, "Carry-save multiplication schemes without final addition," IEEE Trans. on Computers, vol. C-45, pp. 1050-1055, Sep. 1996
[10] O. L. MacSorley, "High-speed arithmetic in binary computers," IRE Proc, vol. 49, pp. 67-91, Jan. 1961
[11] Kei-Yong Khoo, Zhan Yu and Alan N. Willson, Jr., "Improved-Booth encoding for low-power multiplier," IEEE 1996
[12] Edwin de Angel and Earl E. Swartzlander, Jr., "Low power parallel multipliers," IEEE 1996
[13] Ravi K. Kolagotla, Hosahalli R. Srinivas, and Geoffrey F. Burns, "VLSI Implementation of a 200-MHz 16×16 Left-to-Right Carry-Free Multiplier in 0.35μm CMOS Technology for Next-Generation DSPs," IEEE 1997 Custom Integrated Circuits Conference, pp. 469-472
[14] 郑伟等，一种基于标准单元的高性能、低功耗的乘法器设计，待发表
[15] Chip Synthesis Workshop
[16] 遇岩等，高性能Data Path的结构化设计，待发表
[17] 韩晓霞，张明，姚庆栋，“基于．25um工艺的层次式驱动的版图设计”，电路与系统学报，2001年12月，第6卷第4期，Page(s)：51-55
[18] 沈斌华，数字高清晰度电视中解调的设计与ASIC实现，浙江大学硕士毕业论文，2002
[19] Jan M. Rabaey, "Digital Integrated Circuits: A Design Perspective", Prentice Hall, 1996.
[20] Module Compiler Reference Manual, Synopsys, 2001.
[21] Apollo DPII User Guide, Avanti, 2001.
[22] D. E. Thomas, et al., "The Verilog Hardware Description Language", Kluwer Publishers, 1995
[2] "ATSC Digital Television Standard", ATSC Standard A/53, September 16, 1995
[4] “数字电视的进展以及对中国发展数字电视的建议”，徐孟侠，《电视技术》2001年第4期，pp4～11
[5] Advance Digital High Definition System Desrition, David Sarnoff Reserch Center and Philips Laboratories, Jan. 1992
[6] Channel Compatible Digicipjer HDTV System, Submitted by Massachsetts Institute of Technology, on Bahalf of the American Television Alliance, 14, May 1992
[7] 马长华，“八五”期间HDTV科研取得显著成果，广播与电视技术，1996年第6期
[8] 马长华，中国数字化电视广播发展道路，1997-03-20
[9] Special issue on HDTV broadcasting, IEEE Trans. roadcasting, Vol. 37, no.4, pp.121-172, Dec. 1992.
[10] Digicipher HDTV System Description, General Instument Corporation Video Division, Aug.22 1991
[11] ETSI, EN 300 429, Digital Video Broadcasting (DVB): Framing structure, channel coding and modulation for cable systems V1.2.1 (1998-04)
[1] 姚庆栋，梁慧君，戴文琪，《数字无线传输》，浙江大学出版社，1992
[2] R. W. Lucky, J. Salz, and E. J. Weldon, Jr. "Principles of data communication", New York, McGraw-Hill, 1968
[3] 李乐民，叶化祥，《数字传输设备中的均衡器》，人民邮电出版社，1980
[4] S. U. H. Qreshi, "Adaptive Equalization", Proc. IEEE, vol. 3, No. 9, pp.1349-1387, 1985
[5] B. Widrow and M. Hoff, Jr., "Adaptive switching circuits", IRE WESCON Com. Rec. PT4, pp.96-104, 1960
[6] 姚彦等，《数字微波中继通信工程》，人民邮电出版社，1990
[7] 陈尚勤，李晓峰，《快速自适应信息处理》，人民邮电出版社，1993
[8] S. U. H. Qreshi, "Fast start-up equalization with periodic training sequence", IEEE Trans. Inform. Theory, vol. IT-23, pp. 553-563, Sept. 1977.
[9] R. D. Gitlin and S. B. Weistein, "On the required tap-weight precision for digital-implemented adaptive mean square equalizers", B.S.T.J., vol. 58, no. 2, pp. 503-321, Feb. 1979
[10] S. A. Altedar and N.C.Beaulieu, "Upper bounds to the error probability of decision feedback equalization", IEEE Trans. Inform. Theory, vol. 39, no. 1, pp. 145-156, Jan. 1993
[11] 郭梯云等，《数据传输》，人民邮电出版社，1993
[1] Adaptive Equalization, U. H. Qureshi, proceedings of the IEEE, Vol. 73, No. 9, Sep. 1985, pp1349～1387
[2] 《数字无线传输》，姚庆栋，梁慧君，戴文琪，浙江大学出版社，1992年
[3] 陈叔远，颜绍书编著，《相移均衡器》，人民邮电出版社，1984
[4] Self-Recovering Algorithm for Multilevel System, Y. Sato, IEEE Transactions on Communications, June 1975, pp679～682
[5] Blind Equalizers, A. Benveniste, M. Goursat, IEEE Transactions on Communications, Vol. COM-32, No. 8, Aug. 1984, pp871～883
[6] Fast Recovery Equalization Techniques for DTV Signals, N. Deshpande, IEEE Transactions on Broadcasting, Vol. 43, No. 4, Dec. 1997, pp370～377
[7] New Criteria for Blind Deconvolution on Nonminimum Phase Systems (Channels), O. Shalvi, E. Weinstin, IEEE Transactions on Information Theory, Vol. 36, No. 2, March 1990, pp312～321
[8] Admissibility in Blind Adaptive Channel Equalization, C. R. Johnson, IEEE Control Systems, January 1991, pp3～pp15
[9] Adaptive Blind Equalization Coupled With Carrier Recovery for HDTV Modem, Y. S. Choi, H.1 Hwarg, D. I. Song, IEEE Transactions on Consumer Electronics, Vol. 39, No. 3, Aug. 1993, pp384～391
[10] 吴禀圣，HDTV接收系统中的均衡器的设计，浙江大学硕士学位论文，2002
[11] 陈慧芳，HFC网络数字传输技术研究——上行和MAC层研究，浙江大学博士学位论文，2000
[1] 张明，《Verilog HDL实用教程》，电子科技大学出版社，1999．11
[2] Henry Chang, Larry Cooke, Merrill Hunt etc. Surviving the SOC Revolution: a guide to platform-based design. USA: KLUWER Academic Publishers. 1999.31～32.
[3] Petlin, O.; Genusov, A.; Wakeman, L. Methodology and code reuse in the verification of telecommunication SOCs. ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000. Page(s): 187-191.
[4] 韩泽耀，高性能FFT处理器的VLSI实现，浙江大学博士学位论文，2002
[5] 黄国勇，基于IP的SOC设计，世界电子元器件，2001．9
[6] Synopsys MiniDAC 2001, Beijing
[7] 魏少军，SOC设计方法学(一)、(二)，电子产品世界，2001．5
[8] 张纯蓓，IP、SOC与设计技术(一)、(二)，电子产品世界，1999．12
[1] ATSC Standard A/53-1995, ATSC Digital Television Standard.
[2] Qureshi S.U.,Adaptive Equalization, Proc. IEEE, 1985, 73. 1349-1387
[3] 兰景宏，吉利久，IP的复用设计，世界产品与技术，2000，3：8-10
[4] 罗义军，张朝阳，仇佩亮，一种新颖的横向滤波器的优化结构，电路与系统学报，2000，3：22—25
[5] Han, T. and K.A. Carlson. 1987. Fast area-efficient VSLI adders. In: Proceedings, 8th IEEESymposium on Computer Arithmetic, pp 49～56.
[6] Ling, H. 1981. Hign-speed binary adder. IBM Journal of Research and Development, vol.
[7] M. D. Ercegovac and T. Lang, "On-the-fly conversion of redundant into conventional representations," IEEE Trans. on Computer, vol. C-36, no. 7, pp. 895-897, July 1987
[8] M. D. Ercegovac and T. Lang, "Fast multiplication without carry-propagate addition," IEEE Trans. on Computers, vol. C-39, pp. 1385-1390, Nov. 1990
[9] L. Ciminiera and P. Montuschi, "Carry-save multiplication schemes without final addition," IEEE Trans. on Computers, vol. C-45, pp. 1050-1055, Sep. 1996
[10] O. L. MacSorley, "High-speed arithmetic in binary computers," IRE Proc, vol. 49, pp. 67-91, Jan. 1961
[11] Kei-Yong Khoo, Zhan Yu and Alan N. Willson, Jr., "Improved-Booth encoding for low-power multiplier," IEEE 1996
[12] Edwin de Angel and Earl E. Swartzlander, Jr., "Low power parallel multipliers," IEEE 1996
[13] Ravi K. Kolagotla, Hosahalli R. Srinivas, and Geoffrey F. Burns, "VLSI Implementation of a 200-MHz 16×16 Left-to-Right Carry-Free Multiplier in 0.35μm CMOS Technology for Next-Generation DSPs," IEEE 1997 Custom Integrated Circuits Conference, pp. 469-472
[14] 郑伟等，一种基于标准单元的高性能、低功耗的乘法器设计，待发表
[15] Chip Synthesis Workshop
[16] 遇岩等，高性能Data Path的结构化设计，待发表
[17] 韩晓霞，张明，姚庆栋，“基于．25um工艺的层次式驱动的版图设计”，电路与系统学报，2001年12月，第6卷第4期，Page(s)：51-55
[18] 沈斌华，数字高清晰度电视中解调的设计与ASIC实现，浙江大学硕士毕业论文，2002
[19] Jan M. Rabaey, "Digital Integrated Circuits: A Design Perspective", Prentice Hall, 1996.
[20] Module Compiler Reference Manual, Synopsys, 2001.
[21] Apollo DPII User Guide, Avanti, 2001.
[22] D. E. Thomas, et al., "The Verilog Hardware Description Language", Kluwer Publishers, 1995