通信芯片验证方法的研究
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摘要
芯片的验证工作,对提高投片成功率起到关键性作用。有资料显示,造成芯片一次投片成功率低于50%的主要原因就是功能验证还不够完善。根据不同领域的验证对象和不同层次的验证模块,功能验证有很多研究方向,如针对CPU、片上总线、存储器等的验证。由此可见根据研究对象制定验证策略和验证方法对于提高投片成功率具有很大指导意义。
通信芯片一般具有实现收发帧、重传、竞争信道、退避等功能。根据这些特点,它的功能验证需要模拟网络环境中的情况来设计测试用例,验证范围不仅包括芯片自身在竞争到信道后的模块处理情况,还包括在网络中的多站点竞争的情况。针对这些要求论文提出了分阶段的验证策略,第一阶段采用单向施加激励触发的白盒验证方法,第二阶段模拟多站点的网络环境,施加多站点竞争发送数据等测试用例,并应用站点的处理结果触发下一事务的发生,达到循环自触发的半自动化测试。
目前验证技术的发展都是要达到抽象化、自动化、可重用性和可形式化验证等目标。论文研究通信芯片的验证方法也是从上述几方面出发,验证环境采用层次化结构,封装接口引脚并实现功能的事务级抽象;采用加约束的随机生成器产生测试用例,提高验证自动化程度;验证层次中各模型功能独立,便于重用到其他通信芯片或下一代研发产品的验证中;采用SystemVerilog语言搭建验证模型,使用断言来验证协议属性或要求,能够实现部分形式化验证。最后使用结构覆盖率和功能覆盖率相结合的方法分析验证情况,使验证达到工程要求。
Chip verification plays a key part to increase the ratio of taping-out successfully. Some data indicate that the major reason why the ratio of taping-out successfully one-time is below 50% is that function verification is not well done. According to verified objects in different areas and verified modules in different levels, there are many function verification directions, such as CPU, on-chip bus, memory and so on. So making verification strategies and methods according to investigated objects has a great guiding significance.
Generally, communication chips have these functions: frame exchange, re-transmission, channel competition, back off and so on. Based on these characters, test cases must be designed by simulating network environment in the function verification. Not only the chip processing conditions after getting channel competition but also the complicated conditions of multi-station competition are contained in the verification. On these requirements, periods of verification method are presented in this thesis. White box verification method with single direction test cases is taken in the first period. Multi-station network environment is simulated in the second period. Test cases imitating transmitting under multi-station competition are added. The next transaction is triggered by the results which generated by the stations. Half automation is implemented by self-triggered circularly.
At present, abstraction, automation, reusability and easying to formal verification are the verification techniques' goals. In this thesis, research on communication chips' verification methods starts from these aspects too. Multi-level hierarchy is built in the verification, interface pins are packaged and functions are abstracted into transaction level. Test cases are generated by the random number generator with constraints, which increases the automation of verification. Each module in the verification hierarchy is function-independent. It is easy to be reused into other communication chips' verification or next generation products' verification. Verification modules are described by System Verilog, and protocol properties and requirements are verified by assertions, which can realize formal verification partially. Finally, structure coverage and function coverage are combined to analyze the verification, which can make verification meet the engineering requirements.
通信芯片一般具有实现收发帧、重传、竞争信道、退避等功能。根据这些特点,它的功能验证需要模拟网络环境中的情况来设计测试用例,验证范围不仅包括芯片自身在竞争到信道后的模块处理情况,还包括在网络中的多站点竞争的情况。针对这些要求论文提出了分阶段的验证策略,第一阶段采用单向施加激励触发的白盒验证方法,第二阶段模拟多站点的网络环境,施加多站点竞争发送数据等测试用例,并应用站点的处理结果触发下一事务的发生,达到循环自触发的半自动化测试。
目前验证技术的发展都是要达到抽象化、自动化、可重用性和可形式化验证等目标。论文研究通信芯片的验证方法也是从上述几方面出发,验证环境采用层次化结构,封装接口引脚并实现功能的事务级抽象;采用加约束的随机生成器产生测试用例,提高验证自动化程度;验证层次中各模型功能独立,便于重用到其他通信芯片或下一代研发产品的验证中;采用SystemVerilog语言搭建验证模型,使用断言来验证协议属性或要求,能够实现部分形式化验证。最后使用结构覆盖率和功能覆盖率相结合的方法分析验证情况,使验证达到工程要求。
Chip verification plays a key part to increase the ratio of taping-out successfully. Some data indicate that the major reason why the ratio of taping-out successfully one-time is below 50% is that function verification is not well done. According to verified objects in different areas and verified modules in different levels, there are many function verification directions, such as CPU, on-chip bus, memory and so on. So making verification strategies and methods according to investigated objects has a great guiding significance.
Generally, communication chips have these functions: frame exchange, re-transmission, channel competition, back off and so on. Based on these characters, test cases must be designed by simulating network environment in the function verification. Not only the chip processing conditions after getting channel competition but also the complicated conditions of multi-station competition are contained in the verification. On these requirements, periods of verification method are presented in this thesis. White box verification method with single direction test cases is taken in the first period. Multi-station network environment is simulated in the second period. Test cases imitating transmitting under multi-station competition are added. The next transaction is triggered by the results which generated by the stations. Half automation is implemented by self-triggered circularly.
At present, abstraction, automation, reusability and easying to formal verification are the verification techniques' goals. In this thesis, research on communication chips' verification methods starts from these aspects too. Multi-level hierarchy is built in the verification, interface pins are packaged and functions are abstracted into transaction level. Test cases are generated by the random number generator with constraints, which increases the automation of verification. Each module in the verification hierarchy is function-independent. It is easy to be reused into other communication chips' verification or next generation products' verification. Verification modules are described by System Verilog, and protocol properties and requirements are verified by assertions, which can realize formal verification partially. Finally, structure coverage and function coverage are combined to analyze the verification, which can make verification meet the engineering requirements.
引文
[1]马光胜,冯刚.SoC设计与IP核重用技术.北京:国防工业出版社,2006
[2]Gharehbaqhi A M,Yaran B H,Hessabi S,Goudarzi M.An assertion-based verification methodology for system-level design.Computers and Electrical Engineering,2007,Vo133(4):269-284P
[3]Boule M,Zilic Z.Incorporating efficient assertion checkers into hardware emulation.Proceedings of International Conference on Computer Design,2005:221-228P
[4]Bombieri N,Fummi F,Pravadelli G.Fedeli A.Hybrid,incremental assertionbased verification for TLM design flows.IEEE Design.and Test of Computers,2007,Vol24(2):140-152P
[5]Ugarte I,Sanchez P.Assertion checking of behacioral descriptions with nonlinear solver.Proceedings of International Conference on Computer Design,2005:229-231P
[6]边计年,薛宏熙,苏明,吴为民.数字系统设计自动化.北京:清华大学出版社。2005
[7]Qadeer S,Tasiran S.Promising diretions in hardware design verification.Proceedings of International Symposium on Quality Electronic Design,2002:381-387P
[8]Shannon L,Fort B,Parikh S,Patel A,Saldana M,Chow R A system design methodology for reducing system integration time and facilitating modular design verification.Proceedings of International Conference on Field Programmable Logic and Applications,2006:289-294P
[9]沈理.SOC/ASIC设计、验证和测试方法学.广州:中山大学出版社,2D06
[10]Ming Z,Jinian B,Weimin W.Model optimization techniques in a verification platform for classified properties.Proceedings of the First International Conference of Embedded Software and Systems,2005:542-548P
[11]Beckert B,Gladisch C.White-box testing by combining deduction-based specification extraction and black-box testing.Proceedings of the First International Conference on Tests And Proofs,2007:207-216P
[12]Geist D,Biran G.Arons T,Slavkin M,Nustov Y,Farkas M,Holtz K,Long A,King D,Barret S.A methodology for the verification of a "system on chip".Proceedings of the 36~(th) Design Automation Conference,1999:574-579P
[13]Dazhi Y,Dali W,Jiying Z.Event-driven enhanced coverage for sensor networks.Proceedings of the Sixth IASTED International Multi-Conference on Wireless and Optical Communications,2006:377-382P
[14]Rashinkar P,Paterson P,Singh L.System on a Chip:Methodology and Techniques.Kluwer Academic Publishers,2001
[15]卢永江.超大规模集成电路形式验证的方法研究.浙江大学博士学位论文,2005:10-19页
[16]Zhonghai W,Yizheng Y.The improvement for transaction level verification functional coverage.Proceedings of IEEE International Symposium on Circuits and Systems,2005:5850-5853P
[17]Jindal R,Jain K.Verification of transaction-level SystemC model using RTL testbenches.Proceedings of the First ACM and IEEE International Conference on Formal Mthods and Models for Co-Design,2003:199-203P
[18]Langer J,Heinkel U,Jerinic V,Muller D.Inproved coverage driven verification and corner case analysis using decision diagrams.Proceedings of the Sixth International Symposium on Communications and Information Technologies,2006:1179-1184P
[19]Lahbib Y,Missaoui O,Hechkel M,Lahbib D,Mohamedyosri B,Tourki R.Verification flow optimization using an automatic coverage driven testing policy.Porceedings of International Conference on Design and Test of Integrated Systems in Nanoscale Technology,2006:94-99P
[20]Yifan L,Xiaoyang Z,Min W,Jun C,Rencheng B.New methods of FPGA co-verification for SOC.Proceedings of the Sixth International Conference on ASIC,2005:169-172P
[21]Bruce A,Goodenouqh J.Re-useable hardware/software co-verification of IP blocks,Electronic Engineering Design,2002,Vol 908(74):20,23-27P
[22]Jason R A.Hardware/software co-verification.Proceedings of Co-verification of Hardware and Software for ARM SOC Design,2005:119-163P
[23]Edwards M D,Forrest J,Whelan A E.Acceleration of sofrware algorithms using hardware/software co-design techniques.Journal of Systems Architecture,1997,Vol 42(9-10):697-707P
[24]Drusinky D,Man T S.Verification of timing properties in rapid system prototyping.Proceedings of the 14~(th) IEEE International Workshop on Rapid Systems Prototyping,2003:47-53P
[25]Gharehbaqhi A M,Yaran B H,Hessabi S,Goudarzi M.An assertion-based verification metnodology for system-level design.Computers and Electrical Engineering,2007,Vol 33(4):269-284P
[26]Kuangchien C.Assertion-based verification for SOC designs.Proceedings of the Fifth International Conference on ASIC,2003:12-15P
[27]韩俊刚.系统级芯片设计语言和验证语言的发展.现代电子技术,2005,194(3):1-4页
[28]Saqahyroon A,Lakkaraju G;Karunaratne M.A functional verification environment.Proceedings of the 48~(th) IEEE International Midwest Symposium on Circuits and Systems,2005:108-111P
[29]金纯,陈林星,杨吉云.IEEE802.11无线局域网.北京:电子工业出版社,2004
[30]刘乃安.无线局域网(WLAN)-原理、技术与应用.陕西:西安电子科技大学出版社,2004
[31]谢希仁.计算机网络.北京:电子工业出版社,2005
[32]Paul W.A guide to advanced functional verification.Cadence Design Systems Limited,2004
[33]夏宇闻,杨雷,陈先勇,徐伟俊,杨鑫.System Verilog验证方法学.北京:北京航空航天大学出版社,2007
[34]Janick B,Eduard C,Alan H,Andrew N.Verification Methodology Manual for System Verilog.Synopsys Limited and ARM Limited.2006
[35]陈辉,申敏,刘树军.高效验证平台在TD-SCDMA终端芯片功能验证中的应用.重庆邮电学院学报(自然科学版),2006,18(3):299-302页
[2]Gharehbaqhi A M,Yaran B H,Hessabi S,Goudarzi M.An assertion-based verification methodology for system-level design.Computers and Electrical Engineering,2007,Vo133(4):269-284P
[3]Boule M,Zilic Z.Incorporating efficient assertion checkers into hardware emulation.Proceedings of International Conference on Computer Design,2005:221-228P
[4]Bombieri N,Fummi F,Pravadelli G.Fedeli A.Hybrid,incremental assertionbased verification for TLM design flows.IEEE Design.and Test of Computers,2007,Vol24(2):140-152P
[5]Ugarte I,Sanchez P.Assertion checking of behacioral descriptions with nonlinear solver.Proceedings of International Conference on Computer Design,2005:229-231P
[6]边计年,薛宏熙,苏明,吴为民.数字系统设计自动化.北京:清华大学出版社。2005
[7]Qadeer S,Tasiran S.Promising diretions in hardware design verification.Proceedings of International Symposium on Quality Electronic Design,2002:381-387P
[8]Shannon L,Fort B,Parikh S,Patel A,Saldana M,Chow R A system design methodology for reducing system integration time and facilitating modular design verification.Proceedings of International Conference on Field Programmable Logic and Applications,2006:289-294P
[9]沈理.SOC/ASIC设计、验证和测试方法学.广州:中山大学出版社,2D06
[10]Ming Z,Jinian B,Weimin W.Model optimization techniques in a verification platform for classified properties.Proceedings of the First International Conference of Embedded Software and Systems,2005:542-548P
[11]Beckert B,Gladisch C.White-box testing by combining deduction-based specification extraction and black-box testing.Proceedings of the First International Conference on Tests And Proofs,2007:207-216P
[12]Geist D,Biran G.Arons T,Slavkin M,Nustov Y,Farkas M,Holtz K,Long A,King D,Barret S.A methodology for the verification of a "system on chip".Proceedings of the 36~(th) Design Automation Conference,1999:574-579P
[13]Dazhi Y,Dali W,Jiying Z.Event-driven enhanced coverage for sensor networks.Proceedings of the Sixth IASTED International Multi-Conference on Wireless and Optical Communications,2006:377-382P
[14]Rashinkar P,Paterson P,Singh L.System on a Chip:Methodology and Techniques.Kluwer Academic Publishers,2001
[15]卢永江.超大规模集成电路形式验证的方法研究.浙江大学博士学位论文,2005:10-19页
[16]Zhonghai W,Yizheng Y.The improvement for transaction level verification functional coverage.Proceedings of IEEE International Symposium on Circuits and Systems,2005:5850-5853P
[17]Jindal R,Jain K.Verification of transaction-level SystemC model using RTL testbenches.Proceedings of the First ACM and IEEE International Conference on Formal Mthods and Models for Co-Design,2003:199-203P
[18]Langer J,Heinkel U,Jerinic V,Muller D.Inproved coverage driven verification and corner case analysis using decision diagrams.Proceedings of the Sixth International Symposium on Communications and Information Technologies,2006:1179-1184P
[19]Lahbib Y,Missaoui O,Hechkel M,Lahbib D,Mohamedyosri B,Tourki R.Verification flow optimization using an automatic coverage driven testing policy.Porceedings of International Conference on Design and Test of Integrated Systems in Nanoscale Technology,2006:94-99P
[20]Yifan L,Xiaoyang Z,Min W,Jun C,Rencheng B.New methods of FPGA co-verification for SOC.Proceedings of the Sixth International Conference on ASIC,2005:169-172P
[21]Bruce A,Goodenouqh J.Re-useable hardware/software co-verification of IP blocks,Electronic Engineering Design,2002,Vol 908(74):20,23-27P
[22]Jason R A.Hardware/software co-verification.Proceedings of Co-verification of Hardware and Software for ARM SOC Design,2005:119-163P
[23]Edwards M D,Forrest J,Whelan A E.Acceleration of sofrware algorithms using hardware/software co-design techniques.Journal of Systems Architecture,1997,Vol 42(9-10):697-707P
[24]Drusinky D,Man T S.Verification of timing properties in rapid system prototyping.Proceedings of the 14~(th) IEEE International Workshop on Rapid Systems Prototyping,2003:47-53P
[25]Gharehbaqhi A M,Yaran B H,Hessabi S,Goudarzi M.An assertion-based verification metnodology for system-level design.Computers and Electrical Engineering,2007,Vol 33(4):269-284P
[26]Kuangchien C.Assertion-based verification for SOC designs.Proceedings of the Fifth International Conference on ASIC,2003:12-15P
[27]韩俊刚.系统级芯片设计语言和验证语言的发展.现代电子技术,2005,194(3):1-4页
[28]Saqahyroon A,Lakkaraju G;Karunaratne M.A functional verification environment.Proceedings of the 48~(th) IEEE International Midwest Symposium on Circuits and Systems,2005:108-111P
[29]金纯,陈林星,杨吉云.IEEE802.11无线局域网.北京:电子工业出版社,2004
[30]刘乃安.无线局域网(WLAN)-原理、技术与应用.陕西:西安电子科技大学出版社,2004
[31]谢希仁.计算机网络.北京:电子工业出版社,2005
[32]Paul W.A guide to advanced functional verification.Cadence Design Systems Limited,2004
[33]夏宇闻,杨雷,陈先勇,徐伟俊,杨鑫.System Verilog验证方法学.北京:北京航空航天大学出版社,2007
[34]Janick B,Eduard C,Alan H,Andrew N.Verification Methodology Manual for System Verilog.Synopsys Limited and ARM Limited.2006
[35]陈辉,申敏,刘树军.高效验证平台在TD-SCDMA终端芯片功能验证中的应用.重庆邮电学院学报(自然科学版),2006,18(3):299-302页