应用于CMMB锁相环中鉴频鉴相器和电荷泵的设计与研究
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摘要
中国移动多媒体广播(CMMB)是我国自主研发的面向手机等移动终端的无线通信系统,支持多套电视和广播节目,得到了国家广电总局的大力支持,市场前景广阔,然而,在移动终端中的关键模块射频接收机芯片的研发方面国内仍远落后于发达国家,因此研究和设计高性能的接收机芯片具有重要意义。
频率合成器是作为接收机中的重要模块,它的性能指标直接决定了本振信号(LO)的精度和纯度。由于整数分频锁相环的参考频率必须等于信道带宽或者是信道带宽的1/N,而且锁相环的环路带宽不能大于信道带宽的1/10。那么信道带宽对于锁相环环路带宽的限制将会使环路的锁定时间无法满足CMMB通信标准的指标要求。另外,CMMB通信标准还对LO信号的分辨率有一定的指标要求。因此在此次设计的PLL使用了小数分频的结构。
本文主要研究CMMB系统应用的小数分频PLL以及系统中高性能的鉴频鉴相器和电荷泵的实现。
本文的主要工作如下:
首先介绍一些锁相环的一些背景,然后比较整数分频锁相环和小数分频锁相环的区别,从而得到接收机对这两种结构选择的一些依据。然后分析了锁相环中各个模块的工作原理以及它们对锁相环输出的影响。最后详细介绍PLL系统中鉴频鉴相器以及电荷泵在TSMC0.18umCMOS工艺下的设计与实现过程以及仿真结果。
China Mobile Multimedia Broadcasting (CMMB) is China's own R & D for mobile phone and other mobile terminals for wireless communication systems. It supports multiple sets of television and radio programs and strongly supported by the SARFT. But the R & D of the RF receiver chip in the mobile terminal is still far behind developed countries. So it is of crucial importance to research and design high-performance receiver chip.
Synthesizer is an important block in the receiver whose performance is directly related to the accuracy and purity of the local oscillator signals (LO). As the reference frequency of the integer-N Phase-Locked Loop (PLL) must be equal to the channel bandwidth or be one over N of the channel bandwidth and the loop bandwidth of the PLL can’t be larger than the one tenth of the reference frequency. In this case, the limitation on the loop bandwidth will impair the settling time of the PLL and make it impossible to serve the requirement of the CMMB protocol. Besides that, there are also some requirements to the resolution of the LO signals in the CMMB protocol. So we select the fractional-N PLL for our design.
The main aim of this work is to research the fractional-N PLL in the CMMB application and the realization of the high performance PFD and CP of the PLL.
The tasks of this thesis are listed below:
At first, this thesis introduces some background of the PLL and compares the differences between the integer-N PLL and the fractional-N PLL. So it is clear to make a selection between these two topologies for a certain receiver. Then some analyses are followed on the operation principle of each blocks and their influence on the PLL output signals. At last, this thesis introduces the design and realization of the PFD and CP in the TSMC0.18umCMOS process. Simulation results are also followed.
频率合成器是作为接收机中的重要模块,它的性能指标直接决定了本振信号(LO)的精度和纯度。由于整数分频锁相环的参考频率必须等于信道带宽或者是信道带宽的1/N,而且锁相环的环路带宽不能大于信道带宽的1/10。那么信道带宽对于锁相环环路带宽的限制将会使环路的锁定时间无法满足CMMB通信标准的指标要求。另外,CMMB通信标准还对LO信号的分辨率有一定的指标要求。因此在此次设计的PLL使用了小数分频的结构。
本文主要研究CMMB系统应用的小数分频PLL以及系统中高性能的鉴频鉴相器和电荷泵的实现。
本文的主要工作如下:
首先介绍一些锁相环的一些背景,然后比较整数分频锁相环和小数分频锁相环的区别,从而得到接收机对这两种结构选择的一些依据。然后分析了锁相环中各个模块的工作原理以及它们对锁相环输出的影响。最后详细介绍PLL系统中鉴频鉴相器以及电荷泵在TSMC0.18umCMOS工艺下的设计与实现过程以及仿真结果。
China Mobile Multimedia Broadcasting (CMMB) is China's own R & D for mobile phone and other mobile terminals for wireless communication systems. It supports multiple sets of television and radio programs and strongly supported by the SARFT. But the R & D of the RF receiver chip in the mobile terminal is still far behind developed countries. So it is of crucial importance to research and design high-performance receiver chip.
Synthesizer is an important block in the receiver whose performance is directly related to the accuracy and purity of the local oscillator signals (LO). As the reference frequency of the integer-N Phase-Locked Loop (PLL) must be equal to the channel bandwidth or be one over N of the channel bandwidth and the loop bandwidth of the PLL can’t be larger than the one tenth of the reference frequency. In this case, the limitation on the loop bandwidth will impair the settling time of the PLL and make it impossible to serve the requirement of the CMMB protocol. Besides that, there are also some requirements to the resolution of the LO signals in the CMMB protocol. So we select the fractional-N PLL for our design.
The main aim of this work is to research the fractional-N PLL in the CMMB application and the realization of the high performance PFD and CP of the PLL.
The tasks of this thesis are listed below:
At first, this thesis introduces some background of the PLL and compares the differences between the integer-N PLL and the fractional-N PLL. So it is clear to make a selection between these two topologies for a certain receiver. Then some analyses are followed on the operation principle of each blocks and their influence on the PLL output signals. At last, this thesis introduces the design and realization of the PFD and CP in the TSMC0.18umCMOS process. Simulation results are also followed.
引文
[1] Behzad Razavi. RF Microelectronic.北京:清华大学出版社,2003.12,pp.247-254
[2] Chi Baoyong, Yu Zhiping Shi Bingxue,“Analysis and Design of CMOS RF integrated Circuit”,清华大学出版社, 2006
[3] R. Bunch, S. Raman,“Large-signal analysis of MOS varactors in CMOS–Gm LC VCOs”, Journal of Solid-state Circuits, Vol.38, No.8, Aug. 2003.
[4] B. Miller and R. Conley,“A multiple modulator fractional divider,”IEEE Transactions on Instrumentation and Measurement, vol. 40, pp. 578-583, June 1991
[5] M. Copeland, T. Riley, and T. Kwasniewski,“Delta-sigma modulation in fractional-N frequency synthesis,”IEEE Journal of Solid-State Circuits, vol. 28, pp. 553-559, May 1993
[6] RoN. Filiol, T. Riley, C. Plet, and M. Copeland,“An agile ISM band frequency synthesizer with built-in GMSK data modulation,”IEEE Journal of Solid-State Circuits, vol. 33, pp. 998-1008, July 1997
[7] W.Lee, J.D. Cho and S.D. Lee,“A High Speed and Low Power Phase-Frequency Detector and Charge-pump”Proceedings of the ASP-DAC '99.Asia and South Pacific on Design Automation Conference, 18-21 Jan. 1999.
[8] Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang and Wei-Bin Yang,“A DIFFERENCE DETECTOR PFD FOR LOW JITTER PLL”ICECS, vol.1, pp. 43 - 46 Sept. 2001
[9] Yubtzuan Chen, R.; Hong-Yu Huang,“A fast-acquisition CMOS Phase/Frequency Detector”EIT, pp.488– 491, 7-10 May. 2006
[10] M. Mansuri, D. Lin, and C.K. Yang,“Fast Frequency Acquisition Phase-Frequency Detectors for G Samples/s Phase-Locked Loops”, IEEE Journal of solid-state circuit, Vol. 37, NO. 10, 2002.
[11] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic,“digital intergrated circuit—a design perspective”, press, 2004
[12] Chih-Ming Hung,“A Fully Integrated 1.5-V 5.5-GHz CMOS Phase-Locked Loop”IEEE Journal of solid-state circuit, Vol. 37, NO 4, 2002.
[13] H. Kondoh, H. Notani, T. Yoshimura, and Y. Matsuda,“A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector,”IEICE TRANSACTIONS on Electronics Vol.E78-C No.4 pp.381-388, Apr. 20, 1995
[14] Henrik 0. Johansson,“A Simple Precharged CMOS Phase Frequency Detector.,”IEEE Journal of Solid State Circuits, vol. 33, no.2, pp. 295 - 259, Feb. 1998.
[15] W. Rhee,“Design of high-performance CMOS charge pumps in phase locked loops,”in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 545–548, Jul. 1999.
[16] A. Waizman,“A delay line loop for frequency synthesis of de-skewed clock,”in ISSCC Digest of Technical Papers, pp. 298-299, Feb. 1994.
[17] J. Sevenhans, D. Haspeslagh, A. Delarbre, L. Kiss, Z. Chang, and J. F. Kukielka,“An analog radio front-end chip set for a 1.9GHz mobile radio telephone application,”in ISSCC Digest of Technical Papers, pp. 44-45, Feb. 1994.
[18] C. Olgaard, et al.,“Apparatus for reducing power consumption of device controlled bu counter and noise due to counter reload,”Notional Semiconductor Corp., Patent #3341.
[19] V. Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra,“A 320MHz, 1.5mW at 1.35V CMOS PLL for microprocessor clock generation,”in ISSCC Digest of TechnicalPapers, pp. 132-133, Feb. 1996.
[20] A. Waizman,“A delay line loop for frequency synthesis of de-skewed clock,”in ISSCC Digest of Technical Papers, pp. 298-299, Feb. 1994.
[21] J. Sevenhans, D. Haspeslagh, A. Delarbre, L. Kiss, Z. Chang, and J. F. Kukielka,“An analog radio front-end chip set for a 1.9GHz mobile radio telephone application,”in ISSCC Digest of Technical Papers, Feb. 1994, pp. 44-45.
[22] V. Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra,“A 320MHz, 1.5mW at 1.35V CMOS PLL for microprocessor clock generation,”in ISSCC Digest of Technical Papers, Feb. 1996, pp. 132-133.
[23] Robert C.Chang and Lung-Chih Kuo ,“A New Low-Voltage Charge Pump Circuit for PLL,”ISCAS, vol.5, May 2000, pp. 701-704,
[24] Esdras Juárez-Hernández and Alejandro Díaz-Sánchez,“A NOVEL CMOS CHARGE-PUMP CIRCUIT WITH POSITIVE FEEDBACK FOR PLL APPLICATIONS,”ICECS, vol.1, Sept. 2001, pp. 349-352.
[25] Jae-Shin, Min-Sun Keel, Shin-I1 Lim and Suki Kim ,“Charge pump with perfect current matching characteristics in phase-locked loops,”Electronics LETTERS 9th November 2000
[26] Cameron T. Charles, David J. Allstot,“A Buffered Charge Pump with Zero Charge Sharing,”Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on 18-21 May 2008, pp.2633– 2636.
[27] Shiying Han, Jing Jin and Cui Mao,“A Full-Swing Charge Pump with Zero Phase Offset”IEEE PrimeAsia2009, 2009.
[28] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition, John Wiley & Sons Inc, 2002
[29] Alan Hastings, The Art of Analog Layout, Second Edition, Prentice Hall, 2006
[30] MEHMET SOYUER and ROBERT G.,“Frequency Limitation of aconventional Phase-Frequency Detector”IEEE JSSC, vol. 25, NO. 4, august 1990, pp. 1019-1022.
[2] Chi Baoyong, Yu Zhiping Shi Bingxue,“Analysis and Design of CMOS RF integrated Circuit”,清华大学出版社, 2006
[3] R. Bunch, S. Raman,“Large-signal analysis of MOS varactors in CMOS–Gm LC VCOs”, Journal of Solid-state Circuits, Vol.38, No.8, Aug. 2003.
[4] B. Miller and R. Conley,“A multiple modulator fractional divider,”IEEE Transactions on Instrumentation and Measurement, vol. 40, pp. 578-583, June 1991
[5] M. Copeland, T. Riley, and T. Kwasniewski,“Delta-sigma modulation in fractional-N frequency synthesis,”IEEE Journal of Solid-State Circuits, vol. 28, pp. 553-559, May 1993
[6] RoN. Filiol, T. Riley, C. Plet, and M. Copeland,“An agile ISM band frequency synthesizer with built-in GMSK data modulation,”IEEE Journal of Solid-State Circuits, vol. 33, pp. 998-1008, July 1997
[7] W.Lee, J.D. Cho and S.D. Lee,“A High Speed and Low Power Phase-Frequency Detector and Charge-pump”Proceedings of the ASP-DAC '99.Asia and South Pacific on Design Automation Conference, 18-21 Jan. 1999.
[8] Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang and Wei-Bin Yang,“A DIFFERENCE DETECTOR PFD FOR LOW JITTER PLL”ICECS, vol.1, pp. 43 - 46 Sept. 2001
[9] Yubtzuan Chen, R.; Hong-Yu Huang,“A fast-acquisition CMOS Phase/Frequency Detector”EIT, pp.488– 491, 7-10 May. 2006
[10] M. Mansuri, D. Lin, and C.K. Yang,“Fast Frequency Acquisition Phase-Frequency Detectors for G Samples/s Phase-Locked Loops”, IEEE Journal of solid-state circuit, Vol. 37, NO. 10, 2002.
[11] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic,“digital intergrated circuit—a design perspective”, press, 2004
[12] Chih-Ming Hung,“A Fully Integrated 1.5-V 5.5-GHz CMOS Phase-Locked Loop”IEEE Journal of solid-state circuit, Vol. 37, NO 4, 2002.
[13] H. Kondoh, H. Notani, T. Yoshimura, and Y. Matsuda,“A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector,”IEICE TRANSACTIONS on Electronics Vol.E78-C No.4 pp.381-388, Apr. 20, 1995
[14] Henrik 0. Johansson,“A Simple Precharged CMOS Phase Frequency Detector.,”IEEE Journal of Solid State Circuits, vol. 33, no.2, pp. 295 - 259, Feb. 1998.
[15] W. Rhee,“Design of high-performance CMOS charge pumps in phase locked loops,”in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 545–548, Jul. 1999.
[16] A. Waizman,“A delay line loop for frequency synthesis of de-skewed clock,”in ISSCC Digest of Technical Papers, pp. 298-299, Feb. 1994.
[17] J. Sevenhans, D. Haspeslagh, A. Delarbre, L. Kiss, Z. Chang, and J. F. Kukielka,“An analog radio front-end chip set for a 1.9GHz mobile radio telephone application,”in ISSCC Digest of Technical Papers, pp. 44-45, Feb. 1994.
[18] C. Olgaard, et al.,“Apparatus for reducing power consumption of device controlled bu counter and noise due to counter reload,”Notional Semiconductor Corp., Patent #3341.
[19] V. Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra,“A 320MHz, 1.5mW at 1.35V CMOS PLL for microprocessor clock generation,”in ISSCC Digest of TechnicalPapers, pp. 132-133, Feb. 1996.
[20] A. Waizman,“A delay line loop for frequency synthesis of de-skewed clock,”in ISSCC Digest of Technical Papers, pp. 298-299, Feb. 1994.
[21] J. Sevenhans, D. Haspeslagh, A. Delarbre, L. Kiss, Z. Chang, and J. F. Kukielka,“An analog radio front-end chip set for a 1.9GHz mobile radio telephone application,”in ISSCC Digest of Technical Papers, Feb. 1994, pp. 44-45.
[22] V. Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra,“A 320MHz, 1.5mW at 1.35V CMOS PLL for microprocessor clock generation,”in ISSCC Digest of Technical Papers, Feb. 1996, pp. 132-133.
[23] Robert C.Chang and Lung-Chih Kuo ,“A New Low-Voltage Charge Pump Circuit for PLL,”ISCAS, vol.5, May 2000, pp. 701-704,
[24] Esdras Juárez-Hernández and Alejandro Díaz-Sánchez,“A NOVEL CMOS CHARGE-PUMP CIRCUIT WITH POSITIVE FEEDBACK FOR PLL APPLICATIONS,”ICECS, vol.1, Sept. 2001, pp. 349-352.
[25] Jae-Shin, Min-Sun Keel, Shin-I1 Lim and Suki Kim ,“Charge pump with perfect current matching characteristics in phase-locked loops,”Electronics LETTERS 9th November 2000
[26] Cameron T. Charles, David J. Allstot,“A Buffered Charge Pump with Zero Charge Sharing,”Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on 18-21 May 2008, pp.2633– 2636.
[27] Shiying Han, Jing Jin and Cui Mao,“A Full-Swing Charge Pump with Zero Phase Offset”IEEE PrimeAsia2009, 2009.
[28] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition, John Wiley & Sons Inc, 2002
[29] Alan Hastings, The Art of Analog Layout, Second Edition, Prentice Hall, 2006
[30] MEHMET SOYUER and ROBERT G.,“Frequency Limitation of aconventional Phase-Frequency Detector”IEEE JSSC, vol. 25, NO. 4, august 1990, pp. 1019-1022.