摘要
∑-△A/D转换器基于高分辨率、良好的线性度和容易与数字系统集成的优势,广泛应用于音频和电子测量领域。而作为∑-△A/D转换器必不可少的重要组成部分的数字抽取滤波模块,是设计高性能∑-△A/D转换器的关键。
基于∑-△A/D转换器的基本原理与结构,本文广泛深入地研究了数字抽取滤波器的设计方法,提出了五级多采样速率的数字抽取滤波器系统架构:级联积分梳状滤波器+CIC补偿滤波器+两级半带抽取滤波器+直流补偿滤波器。
本设计采用CSD编码、MAG优化、RAG优化、分布式算法和同步流水线技术对抽取滤波模块作优化,进一步简化功能结构,提升抽取滤波运算效率,提升系统工作速度,改善系统整体性能,并减少实现电路所需的硬件资源。
本文所设计的数字抽取滤波模块可实现的分辨率为18-bits,降采样率256倍,信号带宽44kHz,动态范围98dB,信噪比96dB,通带波纹0.05dB。
整个设计经过高效低成本的FPGA仿真验证和Simulink行为级验证,实现了抽取滤波运算速度、功耗和硬件资源的均衡,功能和性能都符合设计预期指标。
Based on the advantages of high-resolution,good linearity and easy to integrated with digital system,∑-△ADC is being widely applied in the audio and electron measurement fields. As an important and necessary component of∑-△ADC, digital decimation filter is the key design of high performance∑-△ADC.
With basic principle and structure of∑-△ADC, this paper presents significant research on the design theory and methods, and proposes a 5-stage multi-sample-rate digital decimation filter: Cascaded Integrator Comb(CIC) Filter+CIC Compensator+2-stage Halfband Decimator+DC Compensator.
The proposed design introduced CSD coding, MAG , RAG, Distributed Arithmetic and synchronous pipeline to optimize the decimation filter module, to simplify the functional structure, to promote the filtering efficiency, to boost the working speed, to improve the performance and to reduce the implementation needed hardware resources.
The implemented device’s typical parameters are 18-bits resolution, 256 downsampling ratio, 44kHz bandwidth, 98dB dynamic range, 96dB SNR and 0.05dB passband ripple.
Having been velidated by effecitive and low-cost FPGA simulation and Simulink’s behavior verification, the whole design has relized a proper trade-off on working speed, power dissipation and hardware resources, the function and performance come up to the expected requirements.
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