摘要
人脸检测是机器视觉的重要组成部分,广泛应用于人机交互,视频监控等领域,而这些应用领域都有嵌入式化的需求,因此如何在嵌入式平台实现实时人脸检测是非常有价值的研究课题。本文使用的AdaBoost人脸检测算法计算复杂,数据访问量大,很难用纯软件方案在嵌入式平台上实时实现。本文提出了一种人脸检测的SoC方案,通过人脸检测加速器提高检测速度。加速器使用阵列单元架构,通过并行和流水等技术大大加速了检测过程。此外优化的窗口扫描策略,可以大大减少加速器对外部数据的访问次数,减轻系统的访存压力。
本文在设计嵌入式人脸检测方案的同时,还给出了一整套基于ESL的嵌入式系统软硬件协同设计的流程。随着SoC设计的复杂度越来越高,设计初期的系统架构设计对最终SoC各方面性能的影响日益增加。SoC系统中软件和硬件结合得更为紧密,需要进行软硬件协同设计和验证。传统的RTL级软硬件协同设计和验证只能在设计的中后期才能进行,不利于尽早发现系统的瓶颈。本文使用先进的电子系统级设计方法,贯穿整个系统的开发过程。首先利用ESL平台分析算法的瓶颈,继而设计合适的软硬件划分方案和软硬件接口。在深入研究系统瓶颈和算法数据流特点后,设计硬件加速器的结构,并利用ESL工具编写硬件加速器的周期级精确模型。在开发过程中,硬件模型逐渐被细化,任何阶段都可将硬件模型集成到ESL平台中,进行系统的软硬件协同设计和验证。
ESL平台的仿真结果显示,带有加速器的嵌入式人脸检测系统与纯软件方案相比有很大的性能提升,可以达到实时检测的速度。本文的工作对人脸检测SoC芯片的研究和设计有很大的参考价值。
Face detection is an important part of computer vision. It is widely used in many fields such as man-machine interaction, video monitoring and etc. However, these fields have more and more requirements of embedded solution. So how to implement real-time face detection on embedded platform is a very valuable research subject. The AdaBoost face detection algorithm in this paper is difficult to implement on embedded platform by software solution due to its high computation load and data throughput. This paper presents a SoC solution for face detection which uses a face detection accelerator to accelerate the detection process. By using the array architecture in the accelerator as well as some pipeline and parallel technologies, face detection is greatly speeded up. Besides, the solution optimizes the strategy of window scanning and decreases the accelerator’s memory accessing for external data. Thus the cost of memory bandwidth is greatly cut down.
While designing an embedded face detection solution, this paper also gives a complete process of SW/HW co-design for embedded system. As the complexity of SoC design increases, system-level design in early development stage is imposing ever more influence on the final SoC’s performance. Software and hardware are so tightly coupled that SW/HW co-simulation is a must in SoC design process. It is difficult to find the performance bottleneck of the system at RTL levels, since co-design and co-verification can only be carried out in later stages of the whole design flow. This paper uses an advanced SW/HW co-design method, Electronic System Level (ESL) design methodology, during the whole development. First use ESL platform to find bottleneck of the algorithm, then design suitable SW/HW partition and interface between software and hardware. After an in-depth study of the system’s bottleneck and the algorithm’s data flow, it designs the structure of the hardware accelerator and develops a cycle-accurate model for the accelerator. The hardware model is gradually refined during the whole develop procedure. And it can be integrated to ESL platform and do SW/HW co-design or co-verification at any stage.
Simulation result on ESL platform shows that embedded face detection with hardware accelerator can get much greater performance than software solution and real-time detection can be achieved. Works in this paper have great value for the research and design of face detection SoCs.
引文
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