摘要
随着半导体与集成电路技术的发展,成百甚至上千的IP核将集成到单个芯片上,使得片上系统(System on Chip,SoC)内部互连结构的吞吐量、延时、功耗、信号完整性以及时钟同步等问题变得更加复杂。传统的基于总线的片上通信结构全局连线长、可扩展性差,成为系统性能的瓶颈。片上网络(Network on Chip,NoC)采用基于数据包的传输方式,为模块之间的互连提供高效、可靠、灵活的通信架构,成为解决复杂SoC设计中全局互连与通信问题的有效方案。由于芯片面积、功耗和性能的约束,片上网络NoC必须针对特定的应用专门定制,这就需要专用片上网络设计方法学。论文对专用片上网络设计中的关键技术进行研究,重点解决了片上网络体系结构建模与性能评估、IP核映射和路径分配、专用拓扑生成以及路由机制设计等关键问题,为建立完整的专用片上网络设计方法学奠定基础。
论文首先从系统级设计角度,提出了一种基于OPNET的NoC建模和仿真方法,用于评估拓扑结构、交换技术和路由算法等设计参数以及不同通信负载和通信模式对NoC体系结构的平均网络延时、吞吐量等性能的影响,为面向特定应用的NoC设计中选择最佳互连体系结构提供依据,并通过将MPEG4解码器映射到NoC体系结构的应用验证了所提出的仿真评估方法的有效性。
在分析建立NoC通信功耗模型的基础上,提出了一种功耗优化的NoC协同映射算法,结合IP核选择和任务分配,实现IP核在NoC体系结构中的自动映射,使得NoC系统全局通信功耗最小。通过多组随机基准实验和一个复杂视频/音频多媒体系统的实际应用验证了算法的性能。实验结果表明,在IP核映射的同时考虑IP核选择和任务分配,与两步式映射、仅有IP核映射相比,可平均节省30%和60%左右的通信功耗。
为解决NoC映射中的核间通信路径分配问题,定义了NoC链路负载均衡性模型,提出了一种NoC路由路径分配方法GAMR,为特定应用的每条通信踪迹生成确定的、无死锁的最短路径路由,在满足带宽约束下,最小化通信功耗,同时保证网络链路负载均衡。采用多组多媒体测试应用实验,验证了GAMR算法性能,与现有NoC映射和路由算法相比,可平均节省20%的功耗和30%的链路带宽需求。
针对专用NoC设计中,规则拓扑结构可能导致大规模冗余路由器、较低链路利用率或者局部拥塞的缺点,深入研究了专用NoC拓扑生成方法。基于NoC映射和路径分配思想,提出了一种层次化拓扑生成方法GATG。该方法以降低网络通信功耗和资源开销为目标,在满足带宽和延时约束下,根据给定应用的通信需求和路由器结构特征,自动将IP核映射到所选路由器单元,同时提出一种基于递归实现的链路构建算法嵌入GATG,用于确定IP核间的通信路径,从而构建路由器之间的拓扑连接链路,最终生成专用的不规则的NoC拓扑结构。GATG生成结果与采用规则2D Mesh结构相比,平均降低通信功耗45%,且可有效节省网络资源开销。论文还进一步提出了一种基于簇划分的NoC拓扑生成算法,简化了GATG方法的实现过程,降低了算法复杂度,且可在通信功耗和网络资源开销方面获得更优的结果。
最后,论文针对NoC全局通信事务管理和可靠性设计问题,提出了“网络监控器”的概念,用于获取全局网络实时负载和可用节点的状态信息及执行路径分配算法。基于网络监控器,提出了一种动态路由机制DyRS-NM。DyRS-NM机制能检测和定位NoC中的拥塞和故障链路,并能区分瞬时和永久性链路故障,采用重传方式避免瞬时错误,通过重新路由计算绕开拥塞和永久性故障链路,解决了高负载下网络拥堵问题,提高了NoC的数据吞吐量以及故障容错能力。论文设计实现了网络监控器和与之通信的容错路由器模块,构建了基于网络监控器的4×4 Mesh结构NoC的RTL级模型,分析了系统性能以及面积功耗开销。相比静态XY路由和动态XY路由,DyRS-NM机制在可接受的开销代价下获得了更优的性能。
System on Chip (SoC) grows in size with the advance of semiconductor technology enabling integration of dozens of cores on a chip. The continuously increasing number of cores makes on chip communication architecture design encounters more complex problems, such as throughput, latency, power, signal integrity and clock synchronization. Traditional bus-based interconnect architectures are inherently non-scalable, making communication a bottleneck. Using data packet transmission scheme, Network on Chip (NoC) provides effective, reliable and flexible infrastructures for system modules, and becoming an effective solution to overcome the problems of global interconnection and communication in complex SoC design. Application-specific NoC is necessary because chip design has constraints of area, power and performance, and design methodologies for application-specific NoC is needed. In this thesis, we study on the key technology of application-sepcific Network on Chip design, and mainly focus on the simulation modeling and performance evaluation of NoC Architectures, IP cores mapping and routing path allocation, application-specific topology generation and routing scheme design. Our work sets an important basis for building complete design methodologies for application-specific NoC.
We firstly propose a modeling and simulation approach based on OPNET from the perspective of system-level design, to evaluate performance of various NoC architectures by varying the network topologies, swiching techniques and routing algorigthms and simulate each of these under different injection rates and traffic patterns. Detailed comparative analysis of the simulation results in terms of average latency and throughput is presented, which could be used as a guideline for NoC designers to make appropriate choices for a given application in order to achieve optimal performance. To further illustrate our evaluation approach, we map a MPEG4 decoder application onto different NoC architectures and show their impact on the NoC system performance.
A NoC co-mapping algorithm for minimizing the overall communication power consumption is proposed, based on the analysis and building of the NoC communication power model. It automatically maps IP cores onto NoC architecture combining IP selection and task assignment. The experiments performed on various random benchmarks and a complex video/audio application to confirm the efficiency of the algorithm. Experimental results show that the proposed algorithm saves about 30% and 60% of power consumption compared to the existing two-step mapping and only IP cores mapping algorithms on average.
To slove the problem of communication path allocation between cores in NoC mapping, we difine the link-balance model, and present a genetic algorithm based mapping and routing approach called GAMR. GAMR generates a deterministic deadlock-free minimal routing path for each communication trace of given application, so as to minimize total communication power consumption and balance the traffic across the links under bandwidth constraint. The evaluation performed on various multimedia benchmark applications confirms the efficiency of the proposed approach. Experimental results show that GAMR saves about 20% of energy consumption and 30% of link bandwidth requirement on average compared to the existing NoC mapping and routing algorithms.
Aiming at the problem of using regular topologies in application-specific NoC design, which may lead to large-scale redundant routers, lower link utilization or local congestion, we further research on application-specific NoC topology generation approachs. Based on the idea of NoC mapping and routing, a genetic algorithm based hierarchical topology generation approach called GATG is proposed. The aim is to reduce the network communication power consumption and resources cost. Under the constraints of the bandwidth and latency, GATG automatically maps IP cores onto the selected routers according to the communication requirements of given application and characteristics of router architectures. In addition, a recursion based routing path construction algorithm embedded in GATG is proposed to construct links between routers, and finally the application-specific irregular NoC topology is formed. Experimental results show that GATG achieves 45% of energy saving on average in comparison with using regular 2D Mesh topology, and also can obtain significant network resources improvement. Furthermore, we present a clustering-based topology generation approach for application-specific NoC. It simplifies the realization of GATG and reduces the complexity of the algorithm, and also can obtain better results in the area of communication power consumption and resources cost.
Finally, from the perspective of the global communication management and reliability design in NoC, we has introduced the concept of network monitor, which monitors overall network real-time conditions and implements path allocation algorithm. Based on the network monitor, a novel dynamic routing scheme called DyRS-NM is presented for NoC application. The proposed scheme DyRS-NM has the ability to discover and deal with both congestion and permanent faults and distinguish them from transient faults. DyRS-NM can avoid transient faults by using retransmisson scheme, and also can detour congested and permanently faulted links by recalculating routing paths. This scheme sloves the problem of network congestion in heavy load, and improves the network throughput and fault tolerance ability. We have finished the circuit design of the network monitor and fault-tolerant router, and built the RTL-level model of network monitor based 4×4 mesh NoC architecture. The system performance and cost of area and power consumption is analysed. Compared to both static and dynamic XY routing, significant performance improvements can be achieved by using the DyRS-NM scheme with acceptable additional cost.
引文
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