Development of a thermal resistance model for chip-on-board packaging of high power LED arrays

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• 作者：Minseok Ha ; Samuel Graham ; ^{sgraham@gatech.edu}
• 刊名：Microelectronics Reliability
• 出版年：2012
• 出版时间：May, 2012
• 年：2012
• 卷：52
• 期：5
• 页码：836-844
• 全文大小：1358 K

文摘

The performance of high power LEDs strongly depends on the junction temperature. Operating at high junction temperature causes degradation of light intensity and lifetime. Therefore, proper thermal management is critical for LED packaging. While the design of the heat sink is a major contributor to lowering the overall thermal resistance of the packaged luminaire, another area of concern arises from the need to address the large heat fluxes that exist beneath the die. In this study we conduct a thermal analysis of high power LED packages implementing chip-on-board (COB) architecture combined with power electronic substrate focusing on heat spreading effect. An analytical thermal resistance model is presented for the LED array and validated by comparing it with finite element analysis (FEA) results. By using the analytical expression of thermal resistance, it is possible to understand the impact of design parameters (e.g., material properties, LED spacing, substrate thickness, etc.) on the package thermal resistance, bypassing the need for detailed computational simulations using FEA.