Multi-level energy/power-aware design methodology for MPSoC

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• 作者：Bassem Ouni^a ; ^{Bassem.Ouni@unice.fr}Author Vitae ; Imen Mhedbi^b ; ^{Imen.Mhedhbi@lip6.fr}Author Vitae ; Chiraz Trabelsi^c ; ^{chiraz.trabelsi@esiea.fr}Author Vitae ; Rabie Ben Atitallah^d ; ^{Rabie.BenAtitallah@univ-valenciennes.fr}Author Vitae ; Cé ; cile Belleudy^a ; ^{Cecile.Belleudy@unice.fr}Author Vitae
• 关键词：Power modeling ; MPSoC ; DVFS ; Design space exploration ; Transactional level ; Functional level
• 刊名：Journal of Parallel and Distributed Computing
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：100
• 期：Complete
• 页码：203-215
• 全文大小：2603 K
• 卷排序：100

文摘

Multi-level design space exploration for Multiprocessor Systems-on-Chip (MPSoC). Design exploration at the functional and transactional level. Integration of runtime power optimization in the design flow. A simulation time of less 1 s at the functional level and 160–190 s at the transactional level. An average error of 1.59% of the transactional level results compared to physical implementations.