A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags in conformance with ISO/IEC 18000-3 protocol

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• 作者：Jian Zhang^a ; ^{bohai@tju.edu.cn" class="auth_mail} ; Wei Zhang^a ; ^{tjuzhangwei@tju.edu.cn" class="auth_mail} ; Yanyan Liu^b ; ^{lyytianjin@nankai.edu.cn" class="auth_mail}
• 关键词：RFID tags ; Analog front-end ; Power management ; ASK demodulator
• 刊名：Microelectronics Journal
• 出版年：June 2014
• 年：2014
• 卷：45
• 期：6
• 页码：578-588
• 全文大小：7864 K

文摘

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip, a high efficiency power management circuit with a rather wide input range is proposed by utilizing 15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag communication. The tag chip is fabricated in 0.18-渭m 2-poly 5-metal mixed signal CMOS technology with EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and reading. The core size of the analog front-end is only 0.94×0.84 mm² with a power consumption of 0.42 mW. Measured results show that the power management circuit is able to maintain a proper working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power consumption of the 10% ASK demodulator is only 690.25 nW.