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High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth
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High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth - Nano Letters (ACS Publications) Subject" content="Bottom-up; VLS; nanowire; III鈭扸; transistor; VLSI" />surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics." />
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Letter

High-Speed Planar GaAs Nanowire Arrays with f<sub>maxsub> > 75 GHz by Wafer-Scale Bottom-up Growth

Xin Miao <sup>鈥?/sup>, Kelson Chabak <sup>鈥?/sup><sup>鈥?/sup>, Chen Zhang <sup>鈥?/sup>, Parsian K. Mohseni <sup>鈥?/sup>, Dennis Walker , Jr.<sup>鈥?/sup>, and Xiuling Li <sup>*sup><sup>鈥?/sup> <sup>鈥?/sup> Microand Nanotechnology Laboratory, Universityof Illinois Urbana鈭扖hampaign, 208 N. Wright Street, Urbana, Illinois 61801, UnitedStates<sup>鈥?/sup> AirForce Research Laboratory, Sensors Directorate, 2241 Avionics Circle, Wright-PattersonAir Force Base, Ohio 45433, United StatesNano Lett., 2015, 15 (5), pp 2780–2786DOI: 10.1021/nl503596jPublication Date (Web): December 10, 2014Copyright 漏 2014 American Chemical Society*E-mail: ailto:xiuling@illinois.edu">xiuling@illinois.edu.

Abstract

Wafer-scale defect-free planar III鈥揤 nanowire (NW) arrays with 鈭?00% yield and precisely defined positions are realized via a patterned vapor鈥搇iquid鈥搒olid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (I<sub>ONsub>/I<sub>OFFsub>), cutoff frequency (f<sub>Tsub>), and maximum oscillation frequency (f<sub>maxsub>) are 10<sup>4sup>, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm<sup>2sup> chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics.

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