A Vertically Integrated Junctionless Nanowire Transistor

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• 作者：Byung-Hyun Lee ; Jae Hur ; Min-Ho Kang ; Tewook Bang ; Dae-Chul Ahn ; Dongil Lee ; Kwang-Hee Kim ; Yang-Kyu Choi
• 刊名：Nano Letters
• 出版年：2016
• 出版时间：March 9, 2016
• 年：2016
• 卷：16
• 期：3
• 页码：1840-1847
• 全文大小：633K
• ISSN：1530-6992

文摘

A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.