Low temperature wafer level conformal polymer dielectric spray coating for through silicon vias with 2:1 aspect ratio

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• 作者：Yuechen Zhuang ; Daquan Yu ; Fengwei Dai ; Zhongcai Niu
• 刊名：Microsystem Technologies
• 出版年：2016
• 出版时间：March 2016
• 年：2016
• 卷：22
• 期：3
• 页码：639-643
• 全文大小：748 KB
• 参考文献：Buchanan K, Burgess S, Giles K, Muggeridge M, Zhao H (2009) Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processing. IEEE Int Conf 3D Syst Integr 1–4
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• 作者单位：Yuechen Zhuang (1) (2)
  Daquan Yu (2)
  Fengwei Dai (1) (2)
  Zhongcai Niu (1)
  
  1. National Center for Advanced Packaging (NCAP China), Building D1, 200 Linghu Avenue, Wuxi, 214135, Jiangsu, People’s Republic of China
  2. Institute of Microelectronics Chinese Academy of Sciences, 3 West Bei-tu-cheng Road, Beijing, 100029, People’s Republic of China
  
• 刊物类别：Engineering
• 刊物主题：Electronics, Microelectronics and Instrumentation
  Nanotechnology
  Mechanical Engineering
  Operating Procedures and Materials Treatment
  
• 出版者：Springer Berlin / Heidelberg
• ISSN：1432-1858

文摘

This paper presents a detailed study to perform low temperature spray coating polymer dielectric process with good conformal deposition on aspect ratio features (2:1) through silicon via (TSV) CMOS image sensor (CIS) wafer-level-packaging. In this study, one kind of phenolic aldehyde polymer is deposited on the sidewall of though silicon via by spray coating process. Individual conditions that affect the weak-point of polymer dielectric on the TSV sidewall and step coverage such as nitrogen gas pressure, polymer so lution flow rate and temperature are investigated. The optimal condition is used to deposit into TSVs by spray coating process. The results turn to give excellent step coverage and satisfied weak-point (>2 µm) on the sidewall of though silicon via with the diameter of 65 µm and depth of 130 µm.