Effects of Elevated Source/Drain and Side Spacer Dielectric on the Drivability Optimization of Non-abrupt Ultra Shallow Junction Gate Underlap DG MOSFETs

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• 作者：Kunal Singh ; Sanjay Kumar ; Ekta Goel ; Balraj Singh…
• 关键词：Elevated source/drain (ES/D) ; ultra shallow junction (USJ) ; straggle parameter ; on/off current ratio ; gate underlap
• 刊名：Journal of Electronic Materials
• 出版年：2017
• 出版时间：January 2017
• 年：2017
• 卷：46
• 期：1
• 页码：520-526
• 全文大小：
• 刊物类别：Chemistry and Materials Science
• 刊物主题：Optical and Electronic Materials; Characterization and Evaluation of Materials; Electronics and Microelectronics, Instrumentation; Solid State Physics;
• 出版者：Springer US
• ISSN：1543-186X
• 卷排序：46

文摘

The effects of drain/source elevation height (h_SD) and side spacer dielectric between the gate and source/drain regions on the drivability performance of the non-abrupt ultra-shallow-junction gate underlap double gate metal oxide field effect transistor of 18 nm gate length has been investigated in terms of the on-state (I_on), off-state (I_off) drain currents, and I_on/I_off ratio. Among the Air, SiO₂, Si₃N_4, and HfO₂ used as spacer dielectrics, while both I_on and I_on/I_off are increased with the elevation height (h_SD) and permittivity of the spacer dielectric, interestingly, an inverse relation between the I_on and I_off for all h_SD below ∼32.5 nm is observed only for the SiO₂ spacer dielectric. Another new observation is the increase in I_off with the h_SD and permittivity of the spacer dielectric due to the enhancement of gate-induced drain leakage current owing to the increased vertical electric field at the drain side. For the most commonly used dielectrics SiO₂ and HfO₂ in the spacer region, the I_on/I_off ratio is increased by ∼277% (at h_SD = 32.5 nm) and ∼516% (at h_SD = 9.5 nm) with respect to their corresponding values at zero elevation, respectively.