A hierarchical multiplier-free architecture for HEVC transform

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• 作者：Chunxiao Fan ; Fu Li ; Guangming Shi ; Yi Niu ; Fei Qi…
• 关键词：DCT ; HEVC ; Multiplier ; free ; Transform coding
• 刊名：Multimedia Tools and Applications
• 出版年：2017
• 出版时间：January 2017
• 年：2017
• 卷：76
• 期：1
• 页码：997-1015
• 全文大小：
• 刊物类别：Computer Science
• 刊物主题：Multimedia Information Systems; Computer Communication Networks; Data Structures, Cryptology and Information Theory; Special Purpose and Application-Based Systems;
• 出版者：Springer US
• ISSN：1573-7721
• 卷排序：76

文摘

In spite of high decorrelation performance, the large block size of transform coding in High Efficiency Video Coding (HEVC) brings about undesirable complexity in hardware design. The heaviest burden in HEVC transform implementation is the large quantity of multiplications. In this paper, we propose a novel hierarchical multiplier-free architecture for HEVC transform, which can achieve a multiplier-free partial butterfly combined with matrix multiplications (PBMM) architecture based on vector decomposition (VD-PBMM). In the proposed architecture, the complicate matrix multiplication in PBMM is achieved by several simple stages to simplify its VLSI realization. Each stage only involves additions and multiplications with power of two which can be achieved by shifters and adders. In addition, the new architecture can balance the distribution of adders to improve the system frequency. The proposed architecture has been evaluated with TSMC 0.13um CMOS technology. The relative system can run at 400 MHz with 92 K logic gates, which is about half of the PBMM method when the latency is 8. The proposed architecture can achieve the transform without any performance loss compared with the standard, and it is suitable for the hardware implementation in VLSI design.