Instruction Fusion for Multiscalar and Many-Core Processors

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• 作者：Yaojie Lu ; Sotirios G. Ziavras
• 关键词：Instruction fusion ; Superscalar ; Benchmarking ; Many ; core processor
• 刊名：International Journal of Parallel Programming
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：45
• 期：1
• 页码：67-78
• 全文大小：
• 刊物类别：Computer Science
• 刊物主题：Theory of Computation; Processor Architectures; Software Engineering/Programming and Operating Systems;
• 出版者：Springer US
• ISSN：1573-7640
• 卷排序：45

文摘

The utilization wall, caused by the breakdown of threshold voltage scaling, hinders performance gains for new generation microprocessors. We propose an instruction fusion technique for multiscalar and many-core processors to alleviate its impact. With instruction fusion, similar copies of an instruction to be run on multiple pipelines or cores are merged into a single copy for simultaneous execution. Instruction fusion applied to vector code enables the processor to idle early pipeline stages and instruction caches at various times during program implementation with minimum performance degradation, while reducing program size and the required instruction memory bandwidth. Instruction fusion is applied here to a MIPS-based dual-core that resembles an ideal multiscalar of degree two. Benchmarking using an FPGA prototype shows a 6–11 % reduction in the dynamic power dissipation for the targeted applications as well as a 17–45 % decrease in code size with frequent performance improvements due to higher instruction cache hit rates.