Capacitive analog front-end circuit with dual-mode automatic parasitic cancellation loop

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• 作者：Yeongjin Mun ; Hyungseup Kim ; Youngwoon Ko ; Yunjong Park…
• 刊名：Microsystem Technologies
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：23
• 期：2
• 页码：515-523
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Electronics and Microelectronics, Instrumentation; Nanotechnology; Mechanical Engineering;
• 出版者：Springer Berlin Heidelberg
• ISSN：1432-1858
• 卷排序：23

文摘

This paper presents a capacitive analog front-end (AFE) integrated circuit (IC) with a dual-mode automatic parasitic cancellation loop. Capacitive AFEs are widely used for various capacitive microsensors based on micro-electro-mechanical system technologies. This paper presents a capacitive AFE IC with a dual-mode automatic parasitic cancellation loop. The capacitive AFE adopts the correlated double-sampling technique for low-noise characteristics. The automatic parasitic cancellation loop removes the unwanted offset caused by the input parasitic capacitances by implementing a successive approximation register scheme. The automatic parasitic cancellation loop includes two parts: a capacitor domain cancellation loop and a charge domain cancellation loop. The capacitor domain loop and charge domain loop execute coarse parasitic and fine parasitic cancellations, respectively. The chip is fabricated using the 0.18-μm complementary metal–oxide–semiconductor process and has an active area of 2.39 mm2. With the dual-mode parasitic cancellation loop, the input parasitic capacitance, ranging from −10.6 to 10.6 pF, can be cancelled with a resolution of 0.224 fF. The measured automatic offset cancellation time is lower than 14 ms. The power consumption is 928 μW with a 3.3 V supply.