Memory-Based Rack Area Networking.

详细信息   

• 作者：Tu ; Cheng-Chun.
• 学历：Doctor
• 年：2014
• 毕业院校：State University of New York
• Department：Computer Science.
• ISBN：9781321101591
• CBH：3631495
• Country：USA
• 语种：English
• FileSize：2837773
• Pages：114

文摘

Cloud-scale data centers increasingly use a rack rather than a machine as the basic building block to provide vital support for applications. To meet the diverse range of service requirements,the concept of disaggregated rack architecture has been proposed recently,in which a rack consists not of a set of self-contained hosts,but of a CPU/memory pool,a disk pool,and a network interface NIC) pool,which are connected through a high-bandwidth and low-latency rack-area network. A major deployment advantage of the disaggregated rack architecture is that it allows different system components,i.e. CPU,memory,disk,and NIC,to be upgraded according to their own technology cycle. By consolidating each type of system components,it also enables more efficient and flexible resource allocation and utilization. This dissertation proposes Marlin,a memory-based rack area network architecture that takes a PCIe-based network,originally designed for intra-host backplane in a single machine and extends it into a inter-host backplane for communication in a data center rack. By virtue of being based on PCIe,Marlin presents a memory-based addressing model for both I/O device sharing among multiple hosts and inter-host communications,and as a result offers hardware-based remote direct memory access HRDMA) as a first-class communications primitive between servers within a rack. Marlin supports socket-based communications for legacy network applications and cross-machine zero memory copying for applications designed specifically to take full advantage of Marlin. Finally,Marlin is positioned as an NFV Network Function Virtualization) platform and proposes a fully direct interrupt delivery hypervisor which minimizes the performance overhead associated with I/O virtualization,a key consideration in NFV. Empirical measurements on a fully operational Marlin prototype based on 4-lane Gen3 PCIe technology show that the one-way kernel-to-kernel latency is 8.5&mgr；sec and the end-to-end sustainable TCP throughput is 19.6 Gbps.