摘要
本论文结合电子所机载合成孔径雷达及其实时数字成像处理器的工程项
目，对成像处理中的方位预处理部分进行了研究，提出了采用子孔径带通滤波
的方位预处理方法，设计了基于CPLD芯片的方位预处理硬件电路。
机载SAR实时数字成像处理的运算量很大，采用子孔径成像方法可以从
方案上实现系统的并行处理，从而提高系统的处理能力。文中对此进行了详细
的分析与讨论。
但是采用子孔径成像方法，会加大方位预处理的工作量。文中详细分析了
方位预处理的工作原理，提出了对子孔径进行带通滤波的处理方法，以有效地
简化方位预处理工作。
可编程逻辑器件（PLD）的应用可以有效提高系统的整体性能。在SAR
信号处理领域以往大多只利用其进行一些简单的逻辑控制，很少用于复杂算法
的实现。随着集成电路技术的发展，PLD性能已经完全能够满足构造复杂系统
的需要。我们在这方面进行了尝试，采用模块化结构与线性流水线处理相结合
的设计思想，设计了基于CPLD芯片EPF10K50VQC240-3的方位预处理器硬
件电路，并将其成功地应用在了机载SAR实时数字成像处理器中，使系统在
物理结构、运算效率、功耗、成本等方面都得到了改进。
这是在电子所内首次利用PLD器件实现信号处理的复杂算法。标志了我
们在硬件设计手段上的一次进步。它不仅改进了现有实时成像处理器系统的性
能，而且积累了可贵的经验，为今后SAR信号处理系统工程设计提供了新的
思路和手段。
This thesis focuses on the azimuth preprocessor in the imaging processor on the basis of the project “A real-time digital imaging processor of air-borne SAR (Synthesis Aperture Radar) system”of IEAS (The Institute of Electronics, Chinese Academy of Sciences). New azimuth preprocess method of band-pass filtering subaperture is proposed. Hardware of azimuth preprocessor is designed and realized with CPLD chip.
The computation amount is large in the real-time digital imaging processor of air-borne SAR. The parallel process structure can be realized by sub-aperture method in system to improve its signal process ability, which is analyzed and discussed detailedly in thesis.
But the sub-aperture method can cause many complexes in azimuth preprocess. We analyze detailedly the azimuth preprocess principle and propose the band-pass filtering sub-aperture method, which can simplify the process effectively.
System performance can be improved by the application of PLD (Programmable Logic Device), which mostly was used in simple circuit control in SAR signal processing field formerly, rarely in complex algorithmic process realization. Along with the development of integrated circuit, PLD has been good enough for realizing complex system now. We explore this point, and design the azimuth preprocessor with the CPLD (Complex Programmable Logic Device) chip of EPFIOK5OVQC24O-3, which is module structured and linear pipeline processed. The application of this design in the real-time imaging processor results in the system performance improvement in many aspects such as the physical structure, run-time efficiency, power consumption and system cost.
The azimuth preprocessor design with CPLD is the first time in realizing complex algorithm with PLD in IEAS. Its success marks our progress in hardware design technique. It not only improves the performance of the existing real-time imaging process system, but also brings us with valuable application experience and new design way in complex signal processing field for SAR system in future.
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