摘要
铁电存储器是将铁电薄膜与传统的硅基半导体集成的新一代可擦写随机存储器，具有非易失、低功耗、高速读写、长寿命和抗辐照等优点，被认为是下一代最具前途的主流存储器之一。目前，我国对铁电存储器的需求十分迫切，而铁电存储器的研制是一个高投入的领域，涉及到材料学、微电子学以及辐射加固等交叉学科，目前我国在铁电存储器的研制方面仍处于基础研究阶段，尚有大量的关键性问题亟待突破与解决。本文围绕高可靠铁电存储器研制领域中若干关键技术进行了深入的研究。
1．基于国内研制条件，成功实现了完整的铁电存储器工艺集成。本文采用射频磁控溅射法，研究了溅射功率对锆钛酸铅（PZT）铁电薄膜性能的影响，得到了最佳的溅射功率；研究了退火温度、保温时间等对薄膜剩余极化强度、漏电流、结晶取向以及表面形貌等的影响，得到了优化的退火条件；突破了小尺寸铁电电容的刻蚀以及消除刻蚀损伤的技术；研究了PZT铁电薄膜在不同热处理环境下铅的挥发性问题以及对底层CMOS器件的影响；研究了还原性氢气气氛对薄膜性能的影响及其防护措施；解决了工艺集成过程中薄膜起泡以及开裂等问题，成功完成了铁电电容工艺与CMOS工艺的集成，为铁电存储器的研制奠定了坚实的基础。
2．验证了修正的铁电电容模型的适用性。对已有模型进行修正，利用此模型，设计并实验验证了2T-2C结构铁电存储单元的读写电路，分析了铁电电容与位线电容的匹配性问题。芯片测试结果表明，集成铁电存储器单元的读写功能正确，不仅成功验证了铁电单元存储过程的有效性和模型的准确性，而且通过调节位线寄生电容大小，可得到最大读出信号差(即读出容差)，因此可用于指导电路设计，提高信号可靠性。在此基础上，设计和优化了1Kbit的并行铁电存储器电路并成功流片。该成果为大容量高可靠铁电存储器的进一步研制奠定了坚实的基础。
3．实验研究了一种新结构的非破坏性读出的铁电场效应晶体管。利用多晶硅/二氧化硅/硅结构具有良好的界面态、漏电流小，以及PZT薄膜在Pt电极上具有良好结晶性能的特点，制备了结构为Pt/PZT/Pt/Ti/Poly-Si/SiO2/Si的铁电场效应晶体管。测试结果表明，该晶体管在±5V的写入电压下，具有1.5V的存储窗口，开/关电流比大于104，栅极漏电流小于10-13A；其次研究了n沟道铁电场效应晶体管的铁电电容与氧化层电容面积比（SOX/SF）对存储窗口的影响。
4．将PZT铁电薄膜应用到LDMOS器件中，首次实现了高压功率器件的存储功能。器件测试结果表明，PZT薄膜不仅使LDMOS器件的耐压提高了3倍，而且该LDMOS在±10V的栅压下，具有2.2V的存储窗口，开/关电流比大于104，表现出良好的存储功能。
5．实验研究了铁电存储器和铁电场效应晶体管的总剂量辐射效应。结果表明，未加固的铁电存储器的抗总剂量能力均低于100krad(Si)。为此，研究了铁电存储器抗总剂量的方法。另外，提出并实验验证了一种可用于高性能铁电存储器设计的加固型NPN管。测试结果表明，在总剂量为100krad(Si)的辐射条件下，所制备的加固型NPN管辐照后的电流增益比常规结构的同比高10%~20%，有效提高了器件的抗总剂量能力，这种加固措施可用于BiCMOS工艺的高性能铁电存储器的设计。
6．分析了铁电存储器单粒子翻转的机理，提出了一种抗单粒子的铁电存储器读出电路器件结构，通过采用部分绝缘硅技术在器件敏感节点引入部分埋氧层，同时采用PN结埋层的方法，可有效降低单粒子瞬态电流脉冲时间和大小，减少积累电荷，降低积累电荷对铁电电容电荷的影响，提高铁电存储器抗单粒子效应的能力，而且可避免自热效应。另外，提出了一种采用双向互锁存结构（DICE）+铁电电容的存储单元结构，该结构具有高抗单粒子翻转的能力和非挥发性的特点，可应用于抗单粒子高速非挥发存储的领域。
Ferroelectric random access memory (FRAM) is a new semiconductor memory, inwhich ferroelectric material is integrated with conventional semiconductor technologyas storage dielectric. Because of the advantages of nonvolatile, low power consumption,fast access time, high endurance and high radiation tolerance, FRAM is regarded as oneof the vigorous next-generation semiconductor memory. Nowadays, the requirement ofFRAM is urgent for China; however, a great number of key technical problems areeager to be solved. Based on the above background，some key research works have beendone in this dissertation aimed at FRAM. The main contents are as following:
1．The integrated process of FRAM is studied and successfully accomplished. Thelead zirconate titanate (PZT) thin films are deposited by the radio frequency magnetronsputtering. The effects of the sputtering power, the annealing method and the annealingtemperature on the PZT film’s performance are studied, including remnant polarization,leak current, crystal phase and so on. The optimized sputtering power and annealingmethod are obtained. The etch technology of PZT film, etching damage andcorresponding recovery methods are investigated by several experiments. The volatilityof lead from the PZT thin film at different temperature has been investigated, and theeffects of ferroelectric capacitors process on the CMOS devices and circuits have beenanalyzed. The hydrogen-induced damage to the PZT film and defendable ways areresearched. Other problems in the integration process, such as the hilloch formation andcrack of the PZT，are analyzed and solved. Based on the optimized fabrication process,ferroelectric device testchips have been realized.
2．Research and testing of FRAM capacitor model and cell signal. The ferroelectriccapacitor model of HSIM is amended by extracting model parameter from the hysteresisloops fabricated by UESTC. Based on the model, the ferroelectric2T-2C memory cell isdesigned and simulated. The affect of the total parasitic capacitance of the bit-line onsensing margin is analyzed. The integrated of ferroelectric process with CMOS processis accomplished and the chips of ferroelectric memory cell are tested. The maximalsensing margin about1.3V is obtained by adjusting parasitic capacitance of the bit-line. The results approves that the read and write operation of this circuit are correct and thesimulated model is accurate. Based on this model,1Kbit FRAM is desiged andoptimized. The FRAM prototypes are tested.
3．A field effect transistor with gate stack of Pt/Pb(Zr_(0.52),Ti_(0.48))O_3/Pt/Ti/Poly-Si/SiO_2/Si is fabricated and tested. I-V and C-V memory window about1.5V are obtainedat a sweep voltage of±5V and an on/off source-drain current ratio of>104is achieved.The relation between the memory windows and the area ratio of SiO2capacitor and PZTcapacitor (SOX/SF) is researched.
4．A novel application of PZT film in high voltage LDMOS device is proposed.The results show that the PZT LDMOS not only achieved triple breakdown voltagecompared with conventional LDMOS with SiO2dielectric, but also has a memorycharacterization. A drain current-gate voltage (Id-Vg) memory window of about2.2Vwas obtained at the sweep voltages of±10V for the350V LDMOS. The retention timeof about270s was recorded for the LDMOS through a controlled Id-Vg measurement.
5．The radiation effects and hardening techniques of FRAM are researched. Atotal-dose hardened NPN bipolar transistor is proposed and fabricated. Theexperimental results indicate that after the radiation total dose of100krad(Si),the currentgain of the hardened NPN is greater10%~20%than the common NPN.
6．The mechanisms of single-event upset in FRAM are analyzed by simulation anda novel single event radiation tolerant CMOS device structure is proposed. The singleevent transient voltage pulses height and width are reduced by introducing partial buriedoxide layer and extra doping layers in sensitive nodes. The structure can availablydecrease SEU sensitivity and alleviate the self-heating. In addition, a new nonvolatileDual Interlocked Cell (NV-DICE) storage element is proposed. The cell includes aDICE latch and four backup ferroelectric capacitors. It can perform store automaticallywhen the power is off abruptly and has high tolerance to SEU. The developed NV-DICEcan be applied to nonvolatile memory device which require high tolerance to SEU.
引文
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