高压集成电路中LDMOS结构在ESD应力下的特性研究
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摘要
自然界中广泛存在的静电放电（ElectroStatic Discharge，ESD）现象是造成芯片失效的一个重要因素。目前集成电路广泛用于各种生活、生产电器中，因此，每年因静电放电造成集成电路的损坏而导致的经济损失非常严重。为了降低由此带来的损失，集成电路的ESD防护能力已是目前芯片设计时必须考虑的问题。近年来随着功率集成电路技术的蓬勃发展，功率集成电路的ESD防护能力也随之越来越得到重视。而以往对芯片ESD问题的研究主要集中于低压电路和器件，对高压集成电路的研究目前还很不成熟。LDMOS （Lateral Diffused MOS）器件由于具有易与CMOS工艺相兼容的特点而被广泛应用于功率集成电路中。研究LDMOS器件所面临的ESD问题对降低研发成本、提高功率集成电路可靠性具有重要意义。
本文基于0.35μm40V/20V/5V BCD（Bipolar/CMOS/DMOS）工艺，使用TCAD仿真分析、器件的TLP （Transmission Line Pulse）与HBM （Human Body Model）测试、失效分析等相结合的研究方法，对LDMOS在ESD大电流注入下的器件特性进行研究，由此提出了器件在宽度方向上的电流不均匀性模型。在此模型的基础上，提出了新的器件结构，并进行实验验证。主要的创新工作和成果如下：
1.基于Kirk效应原理，结合LDMOS体内寄生NPN的电流放大机理，对处于ESD应力下的LDMOS在宽度上的电流不均匀特性进行研究，提出了LDMOS电流不均匀性模型。LDMOS的电流不均匀特性可导致器件只有部分导通，从而限制了器件的抗ESD能力。基于此模型，设计了新型器件结构，通过器件漏端N+用场氧进行隔离，在不增大器件触发电压的情况下增加了器件的镇流电阻，抑制了LDMOS宽度方向上的电流不均匀性，使器件的ESD失效电流从1.06A提升至3.53A。
2.基于LDMOS在大电流注入下发生Kirk效应的理论，分析了LDMOS器件维持电压特性的影响因素，指出了ESD大电流注入条件下Kirk效应将导致LDMOS器件出现维持电压过低现象。基于此原理，提出并验证了一种用于提升器件维持电压的抑制强折回（strong snapback）新结构，并对其ESD特性进行了深入的研究。该结构通过在器件漏端增加一个用于低压PMOS器件的浓度较高的Nwell，使器件漂移区漏端部分的掺杂浓度提升，以提高器件发生Kirk效应的电流密度，从而提升器件维持电压。新器件使维持电压由15V提升至29.8V，并且没有出现严重的折回过程。此外，研究了器件沟道长度、寄生BJT基区接地电阻、电流放大系数等参数对LDMOS器件维持电压特性的影响。通过采用电流放大系数较低的PLDMOS作为ESD保护器件，可得到无折回现象的TLP特性。
3.提出了一种新的NPN-LDMOS结构，并对该器件在ESD应力下的特性进行了深入的研究与验证。该结构通过在LDMOS的漏端增加了一个寄生的低压NPN器件，不仅使LDMOS在ESD应力下的雪崩结由N+/Ndrift转换为N+/Pwell以提高器件的电离碰撞系数，也同时增加了器件的均匀导通特性。相比传统LDMOS，新器件的电流泄放能力由1A提升至3.2A，而其维持电压仅降低约6V。
4.提出了一种用于CMOS芯片I/O引脚的新型SCR结构，并通过实验研究了器件的ESD特性。该SCR不仅可以通过内嵌的MOS器件雪崩击穿触发，还可以通过电源轨之间的寄生电容触发，其抗ESD能力远高于常规的MOS器件，因此可以用较小的器件宽度实现对I/O引脚的ESD保护。在占用面积相近的情况下，I/O引脚的失效电流较MOSFET结构提升了1倍，同时其内嵌的MOS结构可以对电源轨提供基本的ESD防护而几乎不增加占用的芯片面积。
ElectroStatic Discharge (ESD) is still a serious threat to the Integrated Circuit (IC).Since the ICs are widely used in electric equipments, the financial loss caused by ESDis very large. So, ESD robustness of IC has been a problem which must be solved in ICdesign to reduce the related loss. Recently, the ESD robustness of Power IC is animportant research topic with its widely application and rocketing development. Theformer research on the ESD robustness mainly focused on the low voltage ICs anddevices, while for the high voltage ICs, the relative study is still immature. Specifically,LDMOS (Lateral Diffused MOS) is popular in high voltage ICs, because it is prettywell compatible with the CMOS process. So studying the characteristics of the LDMOSunder ESD stress is an important issue to reduce the cost of IC development andimprove the robustness of ICs.
In this dissertation, based on0.35μm40V/20V/5V BCD (Bipolar/CMOS/DMOS)process, the TCAD simulation, TLP (transmission Line Pulse) test, HBM (Human BodyModel) test, and failure analysis were used in order to study the characteristics ofLDMOS under ESD stress. The width direction non-uniform conducting model wasproposed. Based on it, several novel structures were proposed and verified. Thefollowing is the main innovations and results in this dissertation.
1. Based on Kirk effect and the amplification of the parasitic NPN structure, thenon-uniform conducting characteristic in width direction is studied. Then, a model of itis proposed. It can lead to low ESD robustness due to partial device conducting.According to the non-uniform conducting model, a device with high drain ballastresistance is proposed and verified. By splitting the drain N+region with field oxide, itshigh drain ballast resistance can suppress its non-uniform conducting and improve itsESD robustness without increasing the trigger voltage. Its failure current is increasedfrom1.06to3.53A.
2. Based on Kirk effect, the holding voltage of the LDMOS is studied. The lowholding voltage is caused by the Kirk effect under ESD stress. According to it, a novelstrong snapback prevented LDMOS with high holding voltage is proposed and verified.The doping concentration of the part of the drift region near the drain is increased byadding a high concentration Nwell used in the low voltage PMOS device. In the device with high doping concentration drift region, Kirk status needs higher current density.Then, its holding voltage can be increased. The holding voltage of the proposed deviceis increased from15V to29.8V. Besides, no obvious strong snapback is found. Inaddition, since the electron injection from the source to drain influence the holdingvoltage, the influences of the channel length, the resistance in the base region of theparasitic BJT structure, and the current amplification coefficient on the ESDcharacteristics are also studied. A TLP characteristic without snapback can also be gotby using the PLDMOS with low current amplification coefficient as an ESD protectiondevice.
3. A novel NPN-LDMOS structure is proposed. Its characteristics under ESD stressare studied and verified. Compared with the conventional LDMOS, the novel differenceis the added low voltage Pwell in the drain region of the proposed device. Then, aparasitic NPN device is formed in drain region. Under ESD stress, the avalanchegeneration junction in the LDMOS is changed from N+/Ndrift to N+/Pwell, which canlead to higher impact ionization coefficient and more current uniformity. The test resultsshow that its failure current is increased from1A to3.2A at the cost of the holdingvoltage decreased by merely6V.
4. A novel SCR structure is proposed and verified for the I/O pad in CMOS circuits.The SCR can be triggered not only by the avalanche breakdown in the embeddedMOSFET, but also by the parasitic capacitance in the power rails. The device with smallwidth can provide enough ESD protection for the I/O pad, because its robustness ismuch higher than the conventional MOSFET. Its failure current is1time higher than theconventional MOSFET under nearly the same area conditions. Besides, it can alsoprovide basic ESD protection for the power rails by the embedded MOSFET withoutmuch extra area.
本文基于0.35μm40V/20V/5V BCD（Bipolar/CMOS/DMOS）工艺，使用TCAD仿真分析、器件的TLP （Transmission Line Pulse）与HBM （Human Body Model）测试、失效分析等相结合的研究方法，对LDMOS在ESD大电流注入下的器件特性进行研究，由此提出了器件在宽度方向上的电流不均匀性模型。在此模型的基础上，提出了新的器件结构，并进行实验验证。主要的创新工作和成果如下：
1.基于Kirk效应原理，结合LDMOS体内寄生NPN的电流放大机理，对处于ESD应力下的LDMOS在宽度上的电流不均匀特性进行研究，提出了LDMOS电流不均匀性模型。LDMOS的电流不均匀特性可导致器件只有部分导通，从而限制了器件的抗ESD能力。基于此模型，设计了新型器件结构，通过器件漏端N+用场氧进行隔离，在不增大器件触发电压的情况下增加了器件的镇流电阻，抑制了LDMOS宽度方向上的电流不均匀性，使器件的ESD失效电流从1.06A提升至3.53A。
2.基于LDMOS在大电流注入下发生Kirk效应的理论，分析了LDMOS器件维持电压特性的影响因素，指出了ESD大电流注入条件下Kirk效应将导致LDMOS器件出现维持电压过低现象。基于此原理，提出并验证了一种用于提升器件维持电压的抑制强折回（strong snapback）新结构，并对其ESD特性进行了深入的研究。该结构通过在器件漏端增加一个用于低压PMOS器件的浓度较高的Nwell，使器件漂移区漏端部分的掺杂浓度提升，以提高器件发生Kirk效应的电流密度，从而提升器件维持电压。新器件使维持电压由15V提升至29.8V，并且没有出现严重的折回过程。此外，研究了器件沟道长度、寄生BJT基区接地电阻、电流放大系数等参数对LDMOS器件维持电压特性的影响。通过采用电流放大系数较低的PLDMOS作为ESD保护器件，可得到无折回现象的TLP特性。
3.提出了一种新的NPN-LDMOS结构，并对该器件在ESD应力下的特性进行了深入的研究与验证。该结构通过在LDMOS的漏端增加了一个寄生的低压NPN器件，不仅使LDMOS在ESD应力下的雪崩结由N+/Ndrift转换为N+/Pwell以提高器件的电离碰撞系数，也同时增加了器件的均匀导通特性。相比传统LDMOS，新器件的电流泄放能力由1A提升至3.2A，而其维持电压仅降低约6V。
4.提出了一种用于CMOS芯片I/O引脚的新型SCR结构，并通过实验研究了器件的ESD特性。该SCR不仅可以通过内嵌的MOS器件雪崩击穿触发，还可以通过电源轨之间的寄生电容触发，其抗ESD能力远高于常规的MOS器件，因此可以用较小的器件宽度实现对I/O引脚的ESD保护。在占用面积相近的情况下，I/O引脚的失效电流较MOSFET结构提升了1倍，同时其内嵌的MOS结构可以对电源轨提供基本的ESD防护而几乎不增加占用的芯片面积。
ElectroStatic Discharge (ESD) is still a serious threat to the Integrated Circuit (IC).Since the ICs are widely used in electric equipments, the financial loss caused by ESDis very large. So, ESD robustness of IC has been a problem which must be solved in ICdesign to reduce the related loss. Recently, the ESD robustness of Power IC is animportant research topic with its widely application and rocketing development. Theformer research on the ESD robustness mainly focused on the low voltage ICs anddevices, while for the high voltage ICs, the relative study is still immature. Specifically,LDMOS (Lateral Diffused MOS) is popular in high voltage ICs, because it is prettywell compatible with the CMOS process. So studying the characteristics of the LDMOSunder ESD stress is an important issue to reduce the cost of IC development andimprove the robustness of ICs.
In this dissertation, based on0.35μm40V/20V/5V BCD (Bipolar/CMOS/DMOS)process, the TCAD simulation, TLP (transmission Line Pulse) test, HBM (Human BodyModel) test, and failure analysis were used in order to study the characteristics ofLDMOS under ESD stress. The width direction non-uniform conducting model wasproposed. Based on it, several novel structures were proposed and verified. Thefollowing is the main innovations and results in this dissertation.
1. Based on Kirk effect and the amplification of the parasitic NPN structure, thenon-uniform conducting characteristic in width direction is studied. Then, a model of itis proposed. It can lead to low ESD robustness due to partial device conducting.According to the non-uniform conducting model, a device with high drain ballastresistance is proposed and verified. By splitting the drain N+region with field oxide, itshigh drain ballast resistance can suppress its non-uniform conducting and improve itsESD robustness without increasing the trigger voltage. Its failure current is increasedfrom1.06to3.53A.
2. Based on Kirk effect, the holding voltage of the LDMOS is studied. The lowholding voltage is caused by the Kirk effect under ESD stress. According to it, a novelstrong snapback prevented LDMOS with high holding voltage is proposed and verified.The doping concentration of the part of the drift region near the drain is increased byadding a high concentration Nwell used in the low voltage PMOS device. In the device with high doping concentration drift region, Kirk status needs higher current density.Then, its holding voltage can be increased. The holding voltage of the proposed deviceis increased from15V to29.8V. Besides, no obvious strong snapback is found. Inaddition, since the electron injection from the source to drain influence the holdingvoltage, the influences of the channel length, the resistance in the base region of theparasitic BJT structure, and the current amplification coefficient on the ESDcharacteristics are also studied. A TLP characteristic without snapback can also be gotby using the PLDMOS with low current amplification coefficient as an ESD protectiondevice.
3. A novel NPN-LDMOS structure is proposed. Its characteristics under ESD stressare studied and verified. Compared with the conventional LDMOS, the novel differenceis the added low voltage Pwell in the drain region of the proposed device. Then, aparasitic NPN device is formed in drain region. Under ESD stress, the avalanchegeneration junction in the LDMOS is changed from N+/Ndrift to N+/Pwell, which canlead to higher impact ionization coefficient and more current uniformity. The test resultsshow that its failure current is increased from1A to3.2A at the cost of the holdingvoltage decreased by merely6V.
4. A novel SCR structure is proposed and verified for the I/O pad in CMOS circuits.The SCR can be triggered not only by the avalanche breakdown in the embeddedMOSFET, but also by the parasitic capacitance in the power rails. The device with smallwidth can provide enough ESD protection for the I/O pad, because its robustness ismuch higher than the conventional MOSFET. Its failure current is1time higher than theconventional MOSFET under nearly the same area conditions. Besides, it can alsoprovide basic ESD protection for the power rails by the embedded MOSFET withoutmuch extra area.
引文
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